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Searched refs:getLocReg (Results 1 – 25 of 33) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp115 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
166 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
167 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
171 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
172 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
288 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
335 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
336 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp1982 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1998 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1999 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2045 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2046 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2048 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2049 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2066 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2067 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2145 Register DstReg = VA.getLocReg(); in SelectRet()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp803 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
804 VA.getLocReg() == X86::FP1) { in LowerReturn()
818 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
1031 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in getv64i1Argument()
1123 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
1131 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
1140 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
2215 CSInfo.emplace_back(VA.getLocReg(), I); in LowerCall()
2220 switch (VA.getLocReg()) { in LowerCall()
2795 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in IsEligibleForTailCallOptimization()
[all …]
H A DX86FastISel.cpp1239 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1269 Register DstReg = VA.getLocReg(); in X86SelectRet()
1278 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3436 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3437 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3591 Register SrcReg = VA.getLocReg(); in fastLowerCall()
3610 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
186 markPhysRegUsed(VALo.getLocReg()); in assignCustomValue()
187 markPhysRegUsed(VAHi.getLocReg()); in assignCustomValue()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
H A DMipsFastISel.cpp1225 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1226 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1296 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1297 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1722 Register DestReg = VA.getLocReg(); in selectRet()
1763 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3321 Register LocRegLo = VA.getLocReg(); in LowerCall()
3322 Register LocRegHigh = ArgLocs[++i].getLocReg(); in LowerCall()
3363 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3367 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) in LowerCall()
3373 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
3524 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3691 Register ArgReg = VA.getLocReg(); in LowerFormalArguments()
3713 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); in LowerFormalArguments()
3881 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
3885 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
230 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
284 return Loc1.getLocReg() == Loc2.getLocReg(); in resultsCompatible()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp255 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
308 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpack64()
311 if (VA.getLocReg() == CSKY::R3) { in unpack64()
320 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpack64()
468 Register RegLo = VA.getLocReg(); in LowerReturn()
481 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
485 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
585 Register RegLo = VA.getLocReg(); in LowerCall()
613 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
726 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp393 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
469 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
482 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
497 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
648 Register VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
1305 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1322 Register HiReg = VA.getLocReg(); in LowerCall_64()
1323 Register LoReg = VA.getLocReg() + 1; in LowerCall_64()
1343 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
1352 Register Reg = VA.getLocReg(); in LowerCall_64()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp142 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo); in assignCustomValue()
144 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
263 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo); in assignCustomValue()
265 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp325 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
419 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
532 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
703 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
708 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp365 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
476 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
565 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
570 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
603 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp850 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
853 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
1035 MCRegister PhysReg = ArgLoc.getLocReg(); in parametersInCSRMatch()
1116 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp462 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
564 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
568 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
693 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
790 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp655 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
765 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
851 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
948 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h128 Register getLocReg() const { return std::get<Register>(Data); } in getLocReg() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp979 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1072 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1221 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1405 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1410 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1419 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1574 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1680 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1736 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1740 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp681 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
900 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue) in LowerCallResult()
953 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1110 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue); in LowerReturn()
1112 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1337 Register Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp247 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Glue); in LowerReturn()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
375 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
389 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
863 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
864 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp425 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn()
429 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
471 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
724 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
804 Register Reg = VA.getLocReg(); in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4223 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4224 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
4232 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
6041 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
7148 MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_AIX()
7225 const MCPhysReg ArgReg = VA.getLocReg(); in LowerFormalArguments_AIX()
7263 HandleRegLoc(VA.getLocReg(), Offset); in LowerFormalArguments_AIX()
7271 HandleRegLoc(RL.getLocReg(), Offset); in LowerFormalArguments_AIX()
7290 MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_AIX()
7539 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_AIX()
[all …]
H A DPPCFastISel.cpp1516 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1723 Register RetReg = VA.getLocReg(); in SelectRet()
1747 RetRegs.push_back(VA.getLocReg()); in SelectRet()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3063 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3064 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3125 .addReg(VA.getLocReg()); in finishCall()
3126 CLI.InRegs.push_back(VA.getLocReg()); in finishCall()
3882 Register DestReg = VA.getLocReg(); in selectRet()
3925 RetRegs.push_back(VA.getLocReg()); in selectRet()

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