Lines Matching refs:getLocReg

730   RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));  in Passv64i1ArgInRegs()
731 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi)); in Passv64i1ArgInRegs()
765 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg()); in LowerReturn()
789 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
793 X86::FR64XRegClass.contains(VA.getLocReg()) && in LowerReturn()
803 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
804 VA.getLocReg() == X86::FP1) { in LowerReturn()
809 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy)); in LowerReturn()
818 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
839 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg()); in LowerReturn()
841 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy)); in LowerReturn()
1029 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in getv64i1Argument()
1031 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); in getv64i1Argument()
1037 DAG.getCopyFromReg(Root, DL, VA.getLocReg(), MVT::i32, *InGlue); in getv64i1Argument()
1040 DAG.getCopyFromReg(Root, DL, NextVA.getLocReg(), MVT::i32, *InGlue); in getv64i1Argument()
1115 for (MCPhysReg SubReg : TRI->subregs_inclusive(VA.getLocReg())) in LowerCallResult()
1121 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerCallResult()
1123 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
1128 X86::FR64XRegClass.contains(VA.getLocReg()) && in LowerCallResult()
1131 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
1140 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
1155 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InGlue) in LowerCallResult()
1768 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2212 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2215 CSInfo.emplace_back(VA.getLocReg(), I); in LowerCall()
2220 switch (VA.getLocReg()) { in LowerCall()
2795 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in IsEligibleForTailCallOptimization()
2867 Register Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()