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Searched refs:buildInstr (Results 1 – 25 of 40) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h396 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
622 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
630 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
638 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
646 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
893 return buildInstr(Opc, Res, Op).addImm(Val); in buildAssertInstr()
1200 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res}, in buildIsFPClass()
1730 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); in buildCTLZ()
1740 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); in buildCTTZ()
1927 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src}); in buildAbs()
[all …]
H A DCSEMIRBuilder.h95 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp129 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
299 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
397 auto MIB = buildInstr(TargetOpcode::G_BRCOND); in buildBrCond()
424 auto MIB = buildInstr(Opcode); in buildLoadInstr()
454 auto MIB = buildInstr(TargetOpcode::G_STORE); in buildStore()
506 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
547 return buildInstr(Opcode, Res, Op); in buildExtOrTrunc()
591 return buildInstr(Opcode, Dst, Src); in buildCast()
948 auto MIB = buildInstr(Opcode); in buildAtomicRMW()
1055 return buildInstr(TargetOpcode::G_FENCE) in buildFence()
[all …]
H A DCSEMIRBuilder.cpp170 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
278 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
282 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
299 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DIRTranslator.cpp313 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
326 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1570 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1710 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1801 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1946 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
2287 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2325 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER) in translateKnownIntrinsic()
2385 auto Rdx = MIRBuilder.buildInstr( in translateKnownIntrinsic()
2441 MIRBuilder.buildInstr(TargetOpcode::G_SET_FPENV, {}, in translateKnownIntrinsic()
[all …]
H A DLegalizerHelper.cpp1634 .buildInstr( in narrowScalar()
1737 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
1746 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
4832 .buildInstr(ScalarOpc, {NarrowTy}, in fewerElementsVectorReductions()
4871 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, in fewerElementsVectorReductions()
5595 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, in narrowScalarAddSub()
5598 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, in narrowScalarAddSub()
5851 auto Inst = MIRBuilder.buildInstr( in narrowScalarBasic()
6441 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); in lowerRotateWithReverseRotate()
8011 MIRBuilder.buildInstr( in lowerDIVREM()
[all …]
H A DCombinerHelper.cpp1296 auto MIB = Builder.buildInstr(NewOpcode); in applyCombineIndexedLoadStore()
1408 Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM in applyCombineDivRem()
1807 .buildInstr(Opcode, {DestType}, in applyShiftOfShiftedLogic()
1850 B.buildInstr(SrcDef->getOpcode(), {DstReg}, {S1, S2}); in matchCommuteShift()
2449 Builder.buildInstr(SrcExtOp, {DstReg}, {Reg}); in applyCombineExtOfExt()
2483 Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg}); in applyCombineTruncOfExt()
2818 Builder.buildInstr( in applyFunnelShiftConstantModulo()
4147 B.buildInstr(FshOpc, {Dst}, {ShlSrc, LShrSrc, Amt}); in matchOrShiftToFunnelShift()
4712 B.buildInstr(Opc, {DstReg}, {OpLHSLHS, NewCst}); in tryReassocBinOp()
4721 B.buildInstr(Opc, {DstReg}, {NewLHSLHS, OpLHSRHS}); in tryReassocBinOp()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp220 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) in selectShiftMask()
269 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
320 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) in selectSHXADDOp()
587 MachineInstrBuilder PairF64 = MIB.buildInstr( in select()
1110 MachineInstr *Result = MIB.buildInstr(Opc) in selectSelect()
1257 MIB.buildInstr(RISCV::UNIMP, {}, {}); in selectIntrinsicWithSideEffects()
1260 MIB.buildInstr(RISCV::EBREAK, {}, {}); in selectIntrinsicWithSideEffects()
1277 MIB.buildInstr(RISCV::FENCE, {}, {}) in emitFence()
1284 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {}); in emitFence()
1292 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {}); in emitFence()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp466 MIRBuilder.buildInstr(SPIRV::OpStore) in buildAtomicInitInst()
620 MIRBuilder.buildInstr(Opcode) in buildAtomicCompareExchangeInst()
657 MIRBuilder.buildInstr(Opcode) in buildAtomicRMWInst()
1217 MIRBuilder.buildInstr(Opcode) in generateImageMiscQueryInst()
1714 return MIRBuilder.buildInstr(Opcode) in generateEnqueueInst()
1719 return MIRBuilder.buildInstr(Opcode) in generateEnqueueInst()
1726 return MIRBuilder.buildInstr(Opcode) in generateEnqueueInst()
1733 return MIRBuilder.buildInstr(Opcode) in generateEnqueueInst()
1757 return MIRBuilder.buildInstr(Opcode) in generateAsyncCopy()
1767 return MIRBuilder.buildInstr(Opcode) in generateAsyncCopy()
[all …]
H A DSPIRVGlobalRegistry.cpp76 return MIRBuilder.buildInstr(SPIRV::OpTypeBool) in getOpTypeBool()
88 MIRBuilder.buildInstr(SPIRV::OpExtension) in getOpTypeInt()
90 MIRBuilder.buildInstr(SPIRV::OpCapability) in getOpTypeInt()
101 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt) in getOpTypeInt()
110 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat) in getOpTypeFloat()
117 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid) in getOpTypeVoid()
262 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantF) in buildConstantFP()
374 MIRBuilder.buildInstr(SPIRV::OpConstantNull) in getOrCreateIntCompositeOrNull()
432 MIRBuilder.buildInstr(SPIRV::OpConstantNull) in getOrCreateConstNullPtr()
864 return MIRBuilder.buildInstr(SPIRV::OpTypeImage) in getOrCreateOpTypeImage()
[all …]
H A DSPIRVCallLowering.cpp42 return MIRBuilder.buildInstr(SPIRV::OpReturnValue) in lowerReturn()
47 MIRBuilder.buildInstr(SPIRV::OpReturn); in lowerReturn()
361 MIRBuilder.buildInstr(SPIRV::OpFunction) in lowerFormalArguments()
372 MIRBuilder.buildInstr(SPIRV::OpFunctionParameter) in lowerFormalArguments()
387 auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) in lowerFormalArguments()
479 auto MIB = MIRBuilder.buildInstr(SPIRV::OpFunctionCall) in lowerCall()
H A DSPIRVUtils.cpp99 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
116 auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate) in buildOpDecorate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp450 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
465 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
559 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
810 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
934 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
942 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}) in getVectorFCMP()
949 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS}) in getVectorFCMP()
956 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS}) in getVectorFCMP()
963 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS}) in getVectorFCMP()
970 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {RHS, LHS}) in getVectorFCMP()
[all …]
H A DAArch64InstructionSelector.cpp1824 auto Bcc = MIB.buildInstr(AArch64::Bcc) in selectCompareBranch()
3655 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
4919 MIB.buildInstr(CCmpOpc, {}, {LHS}); in emitConditionalComparison()
5263 auto TBL1 = MIB.buildInstr( in selectShuffleVector()
6017 auto Load = MIB.buildInstr(Opc, {Ty}, {Ptr}); in selectVectorLoadIntrinsic()
6061 auto Load = MIB.buildInstr(Opc, {Ty}, {}) in selectVectorLoadLaneIntrinsic()
6126 auto Store = MIB.buildInstr(Opc, {}, {}) in selectVectorStoreLaneIntrinsic()
6151 auto NewI = MIB.buildInstr( in selectIntrinsicWithSideEffects()
6166 MIB.buildInstr(AArch64::BRK, {}, {}) in selectIntrinsicWithSideEffects()
6741 MIB.buildInstr(AArch64::XPACLRI); in selectIntrinsic()
[all …]
H A DAArch64LegalizerInfo.cpp1359 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1463 MIB.buildInstr(Opc, {MI.getOperand(0)}, {MI.getOperand(2)}); in legalizeIntrinsic()
1490 MIB.buildInstr(Opc, {MidTy}, {SrcReg})->getOperand(0).getReg(); in legalizeIntrinsic()
1524 MIB.buildInstr(TargetOpcode::G_FMAXIMUM, {MI.getOperand(0)}, in legalizeIntrinsic()
1527 MIB.buildInstr(TargetOpcode::G_FMINIMUM, {MI.getOperand(0)}, in legalizeIntrinsic()
1530 MIB.buildInstr(TargetOpcode::G_FMAXNUM, {MI.getOperand(0)}, in legalizeIntrinsic()
1533 MIB.buildInstr(TargetOpcode::G_FMINNUM, {MI.getOperand(0)}, in legalizeIntrinsic()
1628 NewI = MIRBuilder.buildInstr(Opcode, {s64, s64}, {}); in legalizeLoadStore()
1633 NewI = MIRBuilder.buildInstr( in legalizeLoadStore()
1892 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {}) in legalizeAtomicCmpxchg128()
[all …]
H A DAArch64PreLegalizerCombiner.cpp331 auto Dot = Builder.buildInstr(DotOpcode, {MidTy}, in applyExtAddvToUdotAddv()
395 .buildInstr(DotOpcode, {MRI.getType(Zeroes)}, in applyExtAddvToUdotAddv()
502 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
513 B.buildInstr(Opc, {addlvTy}, {WorkingRegisters[I]}).getReg(0); in applyExtUaddvToUaddlv()
521 WorkingRegisters[I] = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
525 Register extractReg = B.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, in applyExtUaddvToUaddlv()
547 B.buildInstr(std::get<1>(MatchInfo) ? TargetOpcode::G_SEXT in applyExtUaddvToUaddlv()
644 B.buildInstr(TargetOpcode::G_ADD, {AddDst}, {Op0Wide, Op1Wide}); in tryToSimplifyUADDO()
H A DAArch64CallLowering.cpp418 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
439 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
1077 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
1191 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0); in lowerTailCall()
1279 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
1345 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/GISel/
H A DBPFCallLowering.cpp32 MIRBuilder.buildInstr(BPF::RET); in lowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
617 MachineInstrBuilder PairF64 = B.buildInstr( in select()
806 MachineInstrBuilder MIB = B.buildInstr( in select()
H A DMipsLegalizerInfo.cpp473 if (!MIRBuilder.buildInstr(Opcode) in SelectMSA3OpIntrinsic()
488 MIRBuilder.buildInstr(Opcode) in MSA3OpIntrinsicToGeneric()
500 MIRBuilder.buildInstr(Opcode) in MSA2OpIntrinsicToGeneric()
517 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); in legalizeIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp200 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinToFMaxLegacy()
279 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg}, in applyUCharToFloat()
282 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg}, in applyUCharToFloat()
379 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DAMDGPUPreLegalizerCombiner.cpp195 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16}, in applyClampI64ToI16()
205 auto Med3 = B.buildInstr( in applyClampI64ToI16()
H A DAMDGPUCallLowering.cpp221 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy}, in getStackAddress()
344 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
380 B.buildInstr(AMDGPU::S_ENDPGM) in lowerReturn()
1201 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); in lowerTailCall()
1316 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0); in lowerTailCall()
1437 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP) in lowerCall()
1523 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN) in lowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp323 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
365 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
411 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp209 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
247 MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackSize).addImm(0); in lowerCall()

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