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Searched refs:VecVT (Results 1 – 25 of 32) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2380 VecVT = VecVT.getHalfNumVectorElementsVT(); in decomposeSubvectorInsertExtractToSubRegs()
9191 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT; in lowerReductionSeq()
9371 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
9425 if (VecVT.isFixedLengthVector() && EndIndex == VecVT.getVectorNumElements()) in lowerINSERT_SUBVECTOR()
9474 MVT InterSubVT = VecVT; in lowerINSERT_SUBVECTOR()
9477 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
9547 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerEXTRACT_SUBVECTOR()
9626 MVT InterSubVT = VecVT; in lowerEXTRACT_SUBVECTOR()
9627 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerEXTRACT_SUBVECTOR()
9984 getVSlidedown(DAG, Subtarget, DL, VecVT, DAG.getUNDEF(VecVT), V1, in lowerVECTOR_SPLICE()
[all …]
H A DRISCVISelLowering.h737 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
759 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp370 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
371 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
376 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
397 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
408 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
409 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
416 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
439 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp1461 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1792 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
1793 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
1794 if (VecVT.getScalarSizeInBits() < 8) { in SplitVecRes_INSERT_VECTOR_ELT()
3151 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE() local
3173 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE_SEQ() local
3196 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VP_REDUCE() local
3333 EVT VecVT = Vec.getValueType(); in SplitVecOp_EXTRACT_SUBVECTOR() local
3355 EVT VecVT = Vec.getValueType(); in SplitVecOp_EXTRACT_VECTOR_ELT() local
3379 EVT EltVT = VecVT.getVectorElementType(); in SplitVecOp_EXTRACT_VECTOR_ELT()
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H A DLegalizeVectorOps.cpp574 MVT VecVT = Node->getOperand(1).getSimpleValueType(); in PromoteReduction() local
575 MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT); in PromoteReduction()
618 MVT VecVT = Node->getOperand(0).getSimpleValueType(); in PromoteSETCC() local
619 MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT); in PromoteSETCC()
621 unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in PromoteSETCC()
643 MVT VecVT = Node->getOperand(1).getSimpleValueType(); in PromoteSTRICT() local
644 MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT); in PromoteSTRICT()
646 assert(VecVT.isFloatingPoint()); in PromoteSTRICT()
674 DAG.getNode(ISD::STRICT_FP_ROUND, DL, {VecVT, MVT::Other}, in PromoteSTRICT()
H A DDAGCombiner.cpp22046 EVT VecVT = VecOp.getValueType(); in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts() local
22060 if (VecVT.getScalarType() != ScalarVT) in refineExtractVectorEltIntoMultipleNarrowExtractVectorElts()
22190 EVT VecVT = VecOp.getValueType(); in visitEXTRACT_VECTOR_ELT() local
22226 if (IndexC && VecVT.isFixedLengthVector() && in visitEXTRACT_VECTOR_ELT()
22239 TLI.isTypeLegal(VecVT)) { in visitEXTRACT_VECTOR_ELT()
22241 VecVT.isFixedLengthVector()) && in visitEXTRACT_VECTOR_ELT()
22262 if (VecVT.isScalableVector()) in visitEXTRACT_VECTOR_ELT()
22403 EVT ExtVT = VecVT.getVectorElementType(); in visitEXTRACT_VECTOR_ELT()
22625 if (!isTypeLegal(VecVT) || in reduceBuildVecExtToExtBuildVec()
24031 EVT VecVT = BinOp.getValueType(); in narrowInsertExtractVectorBinOp() local
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H A DLegalizeDAG.cpp1424 EVT VecVT = Vec.getValueType(); in ExpandExtractFromVectorThroughStack() local
1428 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1440 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, in ExpandExtractFromVectorThroughStack()
1445 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandExtractFromVectorThroughStack()
1447 MachinePointerInfo(), VecVT.getVectorElementType(), in ExpandExtractFromVectorThroughStack()
1473 EVT VecVT = Vec.getValueType(); in ExpandInsertToVectorThroughStack() local
1475 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandInsertToVectorThroughStack()
1485 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in ExpandInsertToVectorThroughStack()
H A DSelectionDAG.cpp3835 EVT VecVT = InVec.getValueType(); in computeKnownBits() local
3837 if (VecVT.isScalableVector()) in computeKnownBits()
3839 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); in computeKnownBits()
3840 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in computeKnownBits()
4692 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits() local
4694 if (VecVT.isScalableVector()) in ComputeNumSignBits()
4698 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in ComputeNumSignBits()
5064 EVT VecVT = Op.getOperand(0).getValueType(); in canCreateUndefOrPoison() local
12144 return getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp()
12347 assert(VecVT.getVectorElementCount().isKnownEven() && in SplitEVL()
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H A DTargetLowering.cpp858 EVT VecVT = Vec.getValueType(); in SimplifyMultipleUseDemandedBits() local
859 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && in SimplifyMultipleUseDemandedBits()
1200 EVT VecVT = Vec.getValueType(); in SimplifyDemandedBits() local
1205 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { in SimplifyDemandedBits()
9780 EVT VecVT, const SDLoc &dl, in clampDynamicVectorIndex() argument
9782 assert(!(SubEC.isScalable() && VecVT.isFixedLengthVector()) && in clampDynamicVectorIndex()
9785 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
9789 if (VecVT.isScalableVector() && !SubEC.isScalable()) { in clampDynamicVectorIndex()
9817 DAG, VecPtr, VecVT, in getVectorElementPointer()
9830 EVT EltVT = VecVT.getVectorElementType(); in getVectorSubVecPointer()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4375 if (VecVT.isFloatingPoint()) { in getVCmpInst()
4398 if (VecVT == MVT::v4f32) in getVCmpInst()
4400 else if (VecVT == MVT::v2f64) in getVCmpInst()
4405 if (VecVT == MVT::v4f32) in getVCmpInst()
4407 else if (VecVT == MVT::v2f64) in getVCmpInst()
4412 if (VecVT == MVT::v4f32) in getVCmpInst()
4414 else if (VecVT == MVT::v2f64) in getVCmpInst()
4442 if (VecVT == MVT::v16i8) in getVCmpInst()
4454 if (VecVT == MVT::v16i8) in getVCmpInst()
4466 if (VecVT == MVT::v16i8) in getVCmpInst()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5939 EVT VecVT = Op0.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
6556 if (Op.getValueType() != VecVT) { in combineExtract()
6576 EVT VecVT = Vec.getValueType(); in combineTruncateExtract() local
6577 if (canTreatAsByteVector(VecVT)) { in combineTruncateExtract()
7123 EVT VecVT = Op.getValueType(); in combineEXTRACT_VECTOR_ELT() local
7139 EVT VecVT = Op0.getValueType(); in combineEXTRACT_VECTOR_ELT() local
7388 EVT VecVT = N->getValueType(0); in combineBSWAP() local
7390 if (VecVT != Vec.getValueType()) { in combineBSWAP()
7417 EVT VecVT = N->getValueType(0); in combineBSWAP() local
7418 if (VecVT != Op0.getValueType()) { in combineBSWAP()
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H A DSystemZISelLowering.h721 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
809 MVT VecVT; member
H A DSystemZISelDAGToDAG.cpp1168 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); in loadVectorConstant()
1174 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1176 if (VCI.VecVT == VT.getSimpleVT()) in loadVectorConstant()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp17923 if (VecVT.is256BitVector() || VecVT.is512BitVector()) { in LowerEXTRACT_VECTOR_ELT()
18004 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
18020 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
21872 if (VecVT != CmpVT) in emitOrXorXorTree()
21881 if (VecVT != CmpVT) in emitOrXorXorTree()
43745 if ((VecVT.is256BitVector() || VecVT.is512BitVector()) && in combineExtractWithShuffle()
43756 if ((VecVT == MVT::v4i32 || VecVT == MVT::v2i64) && in combineExtractWithShuffle()
43997 SDValue Lo = getUnpackl(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
43998 SDValue Hi = getUnpackh(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
44026 if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) { in combineArithReduction()
[all …]
H A DX86ISelLoweringCall.cpp1616 MVT VecVT = MVT::Other; in forwardMustTailParameters() local
1621 VecVT = MVT::v16f32; in forwardMustTailParameters()
1623 VecVT = MVT::v8f32; in forwardMustTailParameters()
1625 VecVT = MVT::v4f32; in forwardMustTailParameters()
1631 if (VecVT != MVT::Other) in forwardMustTailParameters()
1632 RegParmTypes.push_back(VecVT); in forwardMustTailParameters()
H A DX86ISelDAGToDAG.cpp425 MVT VecVT = N->getOperand(0).getSimpleValueType(); in getExtractVEXTRACTImmediate() local
426 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getExtractVEXTRACTImmediate()
433 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
434 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getInsertVINSERTImmediate()
441 MVT VecVT = N->getSimpleValueType(0); in getPermuteVINSERTCommutedImmediate() local
1256 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 in PreprocessISelDAG() local
1261 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1263 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1268 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG()
1280 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); in PreprocessISelDAG()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h598 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override { in aggressivelyPreferBuildVectorSources() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp9056 EVT VecVT; in LowerFCOPYSIGN() local
9060 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
9062 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
9069 VecVT = IntVT; in LowerFCOPYSIGN()
9072 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
9075 VecVT = MVT::v4i32; in LowerFCOPYSIGN()
9078 VecVT = MVT::v8i16; in LowerFCOPYSIGN()
14114 assert(VecVT.isFixedLengthVector() && VecVT.isPow2VectorType() && in getVectorBitwiseReduce()
14704 if (VecVT.getScalarType() == MVT::i8 || VecVT.getScalarType() == MVT::i16) in shouldRemoveRedundantExtend()
21342 assert(VecVT.isVector() && VecVT.getVectorElementType() == MVT::i1 && in tryGetOriginalBoolVectorType()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp6724 EVT VecVT = Vec.getValueType(); in lowerINSERT_SUBVECTOR() local
6726 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_SUBVECTOR()
6774 EVT VecVT = Vec.getValueType(); in lowerINSERT_VECTOR_ELT() local
6775 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT()
6776 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT()
6855 EVT VecVT = Vec.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
6856 unsigned VecSize = VecVT.getSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
9226 EVT VecVT = in handleD16VData() local
13065 EVT VecVT = Vec.getValueType(); in shouldExpandVectorDynExt() local
13079 EVT VecVT = Vec.getValueType(); in performExtractVectorEltCombine() local
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H A DAMDGPUISelLowering.h228 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
H A DR600ISelLowering.cpp624 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
625 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
628 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { in vectorToVerticalVector()
633 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6219 EVT VecVT = EVT::getVectorVT( in CombineVMOVDRRCandidateWithVecOp() local
9073 EVT VecVT = VecIn.getValueType(); in LowerINSERT_VECTOR_ELT() local
13364 if (!VecVT.isPow2VectorType() || VecVT.getVectorNumElements() == 1) in PerformVQDMULHCombine()
13376 if (VecVT.getSizeInBits() < 128) { in PerformVQDMULHCombine()
15348 if (!TLI.isTypeLegal(VecVT)) in PerformARMBUILD_VECTORCombine()
15356 SDValue Vec = DAG.getUNDEF(VecVT); in PerformARMBUILD_VECTORCombine()
15522 EVT VecVT = Op0.getValueType(); in PerformExtractEltToVMOVRRD() local
15525 if (VecVT.getVectorNumElements() != 4) in PerformExtractEltToVMOVRRD()
15641 EVT VecVT = Vec.getValueType(); in PerformInsertSubvectorCombine() local
15645 if (!VecVT.isFixedLengthVector() || in PerformInsertSubvectorCombine()
[all …]
H A DARMISelDAGToDAG.cpp4302 EVT VecVT = N->getValueType(0); in Select() local
4303 EVT EltVT = VecVT.getVectorElementType(); in Select()
4304 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
4308 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4314 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4319 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3246 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { in aggressivelyPreferBuildVectorSources() argument
5240 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
5248 SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp410 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
411 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
416 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()

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