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Searched refs:ValueVT (Results 1 – 15 of 15) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp176 if (ValueVT.isVector()) in getCopyFromParts()
185 if (ValueVT.isInteger()) { in getCopyFromParts()
258 if (PartEVT == ValueVT) in getCopyFromParts()
410 if (PartEVT == ValueVT) in getCopyFromPartsVector()
432 if (PartEVT == ValueVT) in getCopyFromPartsVector()
515 if (ValueVT.isVector()) in getCopyToParts()
528 if (PartEVT == ValueVT) { in getCopyToParts()
544 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyToParts()
576 if (PartEVT != ValueVT) { in getCopyToParts()
697 if (PartEVT == ValueVT) { in getCopyToPartsVector()
[all …]
H A DLegalizeTypesGeneric.cpp254 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
279 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
463 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
464 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
475 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
H A DFunctionLoweringInfo.cpp380 for (EVT ValueVT : ValueVTs) { in CreateRegs() local
381 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
383 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
H A DLegalizeVectorTypes.cpp6612 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
6614 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp81 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
82 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp153 EVT ValueVT = LD->getValueType(0); in INITIALIZE_PASS() local
154 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in INITIALIZE_PASS()
158 ValueVT = MVT::i32; in INITIALIZE_PASS()
162 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in INITIALIZE_PASS()
174 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in INITIALIZE_PASS()
476 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
523 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp6195 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
6201 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
6204 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6205 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
6238 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
6269 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
6292 MVT ValueVT = Value.getSimpleValueType(); in Select() local
6297 if (!ValueVT.isVector()) in Select()
6300 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6301 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h589 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1555 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1556 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1567 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1568 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
1571 return DAG.getBitcast(ValueVT, Res); in joinRegisterPartsIntoValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h733 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp19846 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
19847 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
19860 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
19862 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
19899 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
19901 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
19908 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
19912 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
19915 EVT ValueEltVT = ValueVT.getVectorElementType(); in joinRegisterPartsIntoValue()
19921 EVT SameEltTypeVT = ValueVT; in joinRegisterPartsIntoValue()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h913 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4444 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4445 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4446 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4459 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4460 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4461 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4467 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4345 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21488 EVT ValueVT = Value.getValueType(); in performSTORECombine() local
21502 ValueVT.isFixedLengthVector() && in performSTORECombine()
21503 ValueVT.getFixedSizeInBits() >= Subtarget->getMinSVEVectorSizeInBits() && in performSTORECombine()
21523 if (!isHalvingTruncateOfLegalScalableType(ValueVT, StoreVT)) in performSTORECombine()
21577 EVT ValueVT = Value->getValueType(0); in performMSTORECombine() local
21579 if (!isHalvingTruncateOfLegalScalableType(ValueVT, MemVT)) in performMSTORECombine()