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Searched refs:ValueReg (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h49 unsigned ValueReg, unsigned Address,
55 unsigned ValueReg, unsigned Address,
245 unsigned ValueReg, unsigned Address,
253 unsigned ValueReg, unsigned Address,
H A DR600InstrInfo.cpp1089 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1091 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1096 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1112 AddrReg, ValueReg) in buildIndirectWrite()
1121 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1123 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1128 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1144 ValueReg, in buildIndirectRead()
H A DSIRegisterInfo.cpp1221 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1222 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1225 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1534 ? ValueReg in buildSpillLoadStore()
1535 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1569 : ValueReg; in buildSpillLoadStore()
1574 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1584 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1596 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1617 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
[all …]
H A DSIRegisterInfo.h428 unsigned LoadStoreOp, int Index, Register ValueReg,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1288 Register ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1289 if (ValueReg == 0) in selectStore()
1292 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1298 MIB.addReg(ValueReg); in selectStore()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
191 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
221 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp1551 Register ValueReg = BitcastMI->getOperand(2).getReg(); in getBlockStructInstr() local
1552 MachineInstr *ValueMI = MRI->getUniqueVRegDef(ValueReg); in getBlockStructInstr()
1575 Register ValueReg = MI->getOperand(0).getReg(); in getMachineInstrType() local
1577 NextMI->getOperand(1).getReg() != ValueReg) in getMachineInstrType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12032 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
12033 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
12035 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
12036 incr = ValueReg; in EmitPartwordAtomicBinary()
12179 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
12182 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12183 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
12188 .addReg(ValueReg); in EmitPartwordAtomicBinary()
12189 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
12192 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg); in EmitPartwordAtomicBinary()