Lines Matching refs:ValueReg
1207 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1221 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1222 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1225 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1322 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1340 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1534 ? ValueReg in buildSpillLoadStore()
1535 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1568 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1569 : ValueReg; in buildSpillLoadStore()
1574 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1584 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1596 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1617 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1671 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1681 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); in buildSpillLoadStore()