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Searched refs:VSELECT (Results 1 – 25 of 33) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def122 ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp170 setOperationAction(ISD::VSELECT, P, Custom); in initializeHVXLowering()
306 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
439 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
2186 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2472 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd()
2592 SDValue X0 = DAG.getNode(ISD::VSELECT, dl, VecTy, {Q0, B, Zero}); in emitHvxMulLoHiV60()
2810 SDValue Bnd = DAG.getNode(ISD::VSELECT, dl, ResTy, {Neg, M80, M7F}); in ExpandHvxFpToInt()
2814 Int = DAG.getNode(ISD::VSELECT, dl, ResTy, {Pos, Frc14, Bnd}); in ExpandHvxFpToInt()
2819 Int = DAG.getNode(ISD::VSELECT, dl, ResTy, Neg, Zero, Frc23); in ExpandHvxFpToInt()
3186 case ISD::VSELECT: in LowerHvxOperation()
[all …]
H A DHexagonISelLowering.cpp1757 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1758 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1825 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3376 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3489 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3497 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp102 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
344 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
389 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
703 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1038 case ISD::VSELECT: in PerformDAGCombine()
1606 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1621 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1629 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1636 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1667 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd-14.2/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-tqma8mpql.dtsi156 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mn-tqma8mqnl.dtsi191 /* VCC SD IO - switched using SD2 VSELECT */
H A Dimx8mm-tqma8mqml.dtsi201 /* VCC SD IO - switched using SD2 VSELECT */
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h736 VSELECT, enumerator
H A DSelectionDAG.h1239 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
H A DBasicTTIImpl.h1230 ISD = ISD::VSELECT;
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dimx6ul-14x14-evk.dtsi607 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
H A Dimx7-mba7.dtsi486 /* VSELECT */
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp65 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
702 case ISD::VSELECT: in ScalarizeVectorOperand()
992 case ISD::VSELECT: in SplitVectorResult()
3007 case ISD::VSELECT: in SplitVectorOperand()
3138 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
3140 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
4090 case ISD::VSELECT: in WidenVectorResult()
5683 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
6053 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
H A DSelectionDAGDumper.cpp299 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DLegalizeVectorOps.cpp375 case ISD::VSELECT: in LegalizeOp()
910 case ISD::VSELECT: in Expand()
H A DTargetLowering.cpp1664 case ISD::VSELECT: in SimplifyDemandedBits()
3358 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
6761 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
6766 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
7023 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
7049 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
7356 case ISD::VSELECT: { in getNegatedExpression()
9951 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
10041 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
10127 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandShlSat()
H A DSelectionDAG.cpp3398 case ISD::VSELECT: in computeKnownBits()
4232 if (Val.getOpcode() == ISD::SELECT || Val.getOpcode() == ISD::VSELECT) in isKnownToBeAPowerOfTwo()
4462 case ISD::VSELECT: in ComputeNumSignBits()
5256 case ISD::VSELECT: in isKnownNeverZero()
7130 case ISD::VSELECT: in getNode()
12119 case ISD::VSELECT: in UnrollVectorOp()
H A DDAGCombiner.cpp1989 case ISD::VSELECT: return visitVSELECT(N); in visit()
2489 if (N1.getOpcode() != ISD::VSELECT || !N1.hasOneUse()) in foldSelectWithIdentityConstant()
5580 case ISD::VSELECT: in isSaturatingMinMax()
11436 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
12687 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
12708 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes && in tryToFoldExtendSelectLoad()
12709 TLI.getOperationAction(ISD::VSELECT, VT) != TargetLowering::Legal)) in tryToFoldExtendSelectLoad()
13076 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in matchVSelectOpSizesWithSetCC()
13080 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
13103 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
[all …]
H A DLegalizeIntegerTypes.cpp87 case ISD::VSELECT: in PromoteIntegerResult()
1793 case ISD::VSELECT: in PromoteIntegerOperand()
2092 if (N->getOpcode() == ISD::VSELECT) in PromoteIntOp_SELECT()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def707 VP_PROPERTY_FUNCTIONAL_SDOPC(VSELECT)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp190 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
400 setOperationAction(ISD::VSELECT, VT, Legal); in addMVEVectorTypes()
453 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1591 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
13313 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
16957 if (Op0.getOpcode() == ISD::VSELECT && Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16960 if (Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
17131 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17183 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17311 if (Op->getOpcode() == ISD::VSELECT) in PerformVECREDUCE_ADDCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2440 ISD::VSELECT, in X86TargetLowering()
5994 case ISD::VSELECT: in getFauxShuffleMask()
25159 unsigned OpcodeSelect = ISD::VSELECT; in getVectorMaskingNode()
42414 case ISD::VSELECT: in checkBitcastSrcVectorSize()
42486 case ISD::VSELECT: in signExtendBitcastSrcVector()
43884 if (Vec.getOpcode() == ISD::VSELECT && in scalarizeExtEltFP()
44438 if (N->getOpcode() != ISD::VSELECT) in combineVSelectWithAllOnesOrZeros()
44642 if ((N->getOpcode() != ISD::VSELECT && in combineVSelectToBLENDV()
44795 if (N->getOpcode() != ISD::VSELECT) in commuteSelect()
55116 case ISD::VSELECT: in combineConcatVectorOps()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp532 ISD::USHLSAT, ISD::USUBO, ISD::USUBO_CARRY, ISD::VSELECT, in NVPTXTargetLowering()
727 ISD::VSELECT}); in NVPTXTargetLowering()
5684 case ISD::VSELECT: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1009 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
1714 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
1942 setOperationAction(ISD::VSELECT, VT, Custom); in addTypeForFixedLengthSVE()
6356 case ISD::VSELECT: in LowerOperation()
9782 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
20258 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
22389 if (FirstUse->getOpcode() != ISD::VSELECT) in tryToWidenSetCCOperands()
22759 return DAG.getNode(ISD::VSELECT, SDLoc(N), NTy, in trySwapVSelectOperands()
22831 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
23909 case ISD::VSELECT: in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp734 {ISD::SELECT_CC, ISD::VSELECT, ISD::VP_MERGE, ISD::VP_SELECT}, VT, in RISCVTargetLowering()
1193 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
1251 {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT, in RISCVTargetLowering()
1306 setOperationAction({ISD::VSELECT, ISD::SELECT}, VT, Custom); in RISCVTargetLowering()
3440 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBuildVectorViaDominantValues()
4961 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
6600 case ISD::VSELECT: in LowerOperation()
7194 return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV); in lowerSELECT()
7588 return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); in lowerVectorMaskExt()

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