Lines Matching refs:VSELECT
190 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
400 setOperationAction(ISD::VSELECT, VT, Legal); in addMVEVectorTypes()
453 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1591 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
8600 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
10269 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD()
13313 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
13446 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
16957 if (Op0.getOpcode() == ISD::VSELECT && Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16960 if (Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16970 return DAG.getNode(ISD::VSELECT, DL, VT, Op1.getOperand(0), FAdd, Op0, FaddFlags); in PerformFAddVSelectCombine()
17131 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17183 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17311 if (Op->getOpcode() == ISD::VSELECT) in PerformVECREDUCE_ADDCombine()
17320 Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0), in PerformVECREDUCE_ADDCombine()
18863 case ISD::VSELECT: return PerformVSELECTCombine(N, DCI, Subtarget); in PerformDAGCombine()