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Searched refs:VReg (Results 1 – 25 of 140) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp38 VRegDefMap[Key] = VReg; in getOrCreateVReg()
39 VRegUpwardsUse[Key] = VReg; in getOrCreateVReg()
40 return VReg; in getOrCreateVReg()
60 VRegDefUses[Key] = VReg; in getOrCreateVRegDefAt()
61 setCurrentVReg(MBB, Val, VReg); in getOrCreateVRegDefAt()
62 return VReg; in getOrCreateVRegDefAt()
72 Register VReg = getOrCreateVReg(MBB, Val); in getOrCreateVRegUseAt() local
73 VRegDefUses[Key] = VReg; in getOrCreateVRegUseAt()
74 return VReg; in getOrCreateVRegUseAt()
261 Register VReg = Use.second; in propagateVRegs() local
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H A DMIRVRegNamerUtils.cpp49 for (const auto &VReg : VRegs) { in getVRegRenameMap() local
50 const unsigned Reg = VReg.getReg(); in getVRegRenameMap()
51 VRM[Reg] = createVirtualRegisterWithLowerName(Reg, GetUniqueVRegName(VReg)); in getVRegRenameMap()
141 unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { in createVirtualRegister() argument
142 assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers"); in createVirtualRegister()
143 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
144 return createVirtualRegisterWithLowerName(VReg, Name); in createVirtualRegister()
168 unsigned VRegRenamer::createVirtualRegisterWithLowerName(unsigned VReg, in createVirtualRegisterWithLowerName() argument
171 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in createVirtualRegisterWithLowerName()
173 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName); in createVirtualRegisterWithLowerName()
H A DLiveRangeEdit.cpp36 Register VReg = MRI.cloneVirtualRegister(OldReg); in createEmptyIntervalFrom() local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createEmptyIntervalFrom()
40 LiveInterval &LI = LIS.createEmptyInterval(VReg); in createEmptyIntervalFrom()
56 Register VReg = MRI.cloneVirtualRegister(OldReg); in createFrom() local
67 LIS.getInterval(VReg).markNotSpillable(); in createFrom()
68 return VReg; in createFrom()
453 Register VReg = LI->reg(); in eliminateDeadDefs() local
455 TheDelegate->LRE_WillShrinkVirtReg(VReg); in eliminateDeadDefs()
463 if (llvm::is_contained(RegsBeingSpilled, VReg)) in eliminateDeadDefs()
478 if (Original != VReg && Original != 0) in eliminateDeadDefs()
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H A DRegAllocPBQP.cpp334 LiveInterval &LI = LIS.getInterval(VReg); in apply()
604 Register VReg = Worklist.back(); in initializeGraph() local
663 auto VReg = KV.first; in initializeGraph() local
666 if (LIS.getInterval(VReg).empty()) { in initializeGraph()
667 EmptyIntervalVRegs.insert(VReg); in initializeGraph()
668 VRegsToAlloc.erase(VReg); in initializeGraph()
683 G.getNodeMetadata(NId).setVReg(VReg); in initializeGraph()
686 G.getMetadata().setNodeIdForVReg(VReg, NId); in initializeGraph()
690 void RegAllocPBQP::spillVReg(Register VReg, in spillVReg() argument
694 VRegsToAlloc.erase(VReg); in spillVReg()
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H A DLiveIntervalUnion.cpp159 const LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
160 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
161 RecentReg = VReg; in collectInterferingVRegs()
162 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
H A DRegisterScavenging.cpp340 Register VReg, bool ReserveAfter) { in scavengeVReg() argument
347 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) { in scavengeVReg()
354 if (!MI.readsRegister(VReg, &TRI)) { in scavengeVReg()
371 MRI.def_operands(VReg), [VReg, &TRI](const MachineOperand &MO) { in scavengeVReg()
372 return !MO.getParent()->readsRegister(VReg, &TRI); in scavengeVReg()
381 const TargetRegisterClass &RC = *MRI.getRegClass(VReg); in scavengeVReg()
384 MRI.replaceRegWith(VReg, SReg); in scavengeVReg()
H A DMachineRegisterInfo.cpp170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister() argument
173 VRegInfo[Reg].first = VRegInfo[VReg].first; in cloneVirtualRegister()
174 setType(Reg, getType(VReg)); in cloneVirtualRegister()
175 noteCloneVirtualRegister(Reg, VReg); in cloneVirtualRegister()
179 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType() argument
180 VRegToType.grow(VReg); in setType()
181 VRegToType[VReg] = Ty; in setType()
449 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
451 if (LI.second == VReg) in getLiveInPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp92 Register VReg = Register::index2VirtReg(VRegIdx); in runOnMachineFunction() local
94 if (MRI.use_empty(VReg)) in runOnMachineFunction()
97 if (MFI.isVRegStackified(VReg)) { in runOnMachineFunction()
98 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " in runOnMachineFunction()
100 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); in runOnMachineFunction()
103 if (MFI.getWAReg(VReg) == WebAssembly::UnusedReg) { in runOnMachineFunction()
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); in runOnMachineFunction()
105 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction() local
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
89 VReg = MRI.createVirtualRegister(RC); in runOnMachineFunction()
93 FI->setFrameBaseVreg(VReg); in runOnMachineFunction()
95 dbgs() << "replacing preg " << PReg << " with " << VReg << " (" in runOnMachineFunction()
96 << Register::virtReg2Index(VReg) << ")\n"; in runOnMachineFunction()
100 MO.setReg(VReg); in runOnMachineFunction()
H A DWebAssemblyMachineFunctionInfo.h122 void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg) { in stackifyVReg() argument
123 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
124 auto I = Register::virtReg2Index(VReg); in stackifyVReg()
129 void unstackifyVReg(unsigned VReg) { in unstackifyVReg() argument
130 auto I = Register::virtReg2Index(VReg); in unstackifyVReg()
134 bool isVRegStackified(unsigned VReg) const { in isVRegStackified() argument
135 auto I = Register::virtReg2Index(VReg); in isVRegStackified()
142 void setWAReg(unsigned VReg, unsigned WAReg) { in setWAReg() argument
144 auto I = Register::virtReg2Index(VReg); in setWAReg()
148 unsigned getWAReg(unsigned VReg) const { in getWAReg() argument
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H A DWebAssemblyRegColoring.cpp67 unsigned VReg) { in computeWeight() argument
69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) in computeWeight()
253 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
254 if (MFI.isVRegStackified(VReg)) in runOnMachineFunction()
257 if (MRI->use_empty(VReg)) in runOnMachineFunction()
260 LiveInterval *LI = &Liveness->getInterval(VReg); in runOnMachineFunction()
262 LI->setWeight(computeWeight(MRI, MBFI, VReg)); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h768 void setType(Register VReg, LLT Ty);
795 assert(VReg.isVirtual()); in setRegAllocationHint()
796 RegAllocHints[VReg].first = Type; in setRegAllocationHint()
797 RegAllocHints[VReg].second.clear(); in setRegAllocationHint()
804 assert(VReg.isVirtual()); in addRegAllocationHint()
814 void clearSimpleHint(Register VReg) { in clearSimpleHint() argument
817 RegAllocHints[VReg].second.clear(); in clearSimpleHint()
824 assert(VReg.isVirtual()); in getRegAllocationHint()
833 assert(VReg.isVirtual()); in getSimpleHint()
842 assert(VReg.isVirtual()); in getRegAllocationHints()
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H A DRegAllocPBQP.h148 void setNodeIdForVReg(Register VReg, GraphBase::NodeId NId) { in setNodeIdForVReg() argument
149 VRegToNodeId[VReg.id()] = NId; in setNodeIdForVReg()
152 GraphBase::NodeId getNodeIdForVReg(Register VReg) const { in getNodeIdForVReg() argument
153 auto VRegItr = VRegToNodeId.find(VReg); in getNodeIdForVReg()
187 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg), in NodeMetadata()
203 void setVReg(Register VReg) { this->VReg = VReg; } in setVReg() argument
204 Register getVReg() const { return VReg; } in getVReg()
262 Register VReg; variable
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h106 SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
111 SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
114 Register VReg, MachineInstr &I,
119 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
149 SPIRVType *getSPIRVTypeForVReg(Register VReg) const;
152 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg() argument
153 return getSPIRVTypeForVReg(VReg) != nullptr; in hasSPIRVTypeForVReg()
163 bool isScalarOfType(Register VReg, unsigned TypeOpcode) const;
168 bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const;
177 SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const;
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp280 return VReg; in getVR()
334 VReg = NewVReg; in AddRegisterOperand()
385 Register VReg = R->getReg(); in AddOperand() local
401 VReg = NewVReg; in AddOperand()
461 return VReg; in ConstrainForSubReg()
469 .addReg(VReg); in ConstrainForSubReg()
619 NewVReg).addReg(VReg); in EmitCopyToRegClassNode()
821 unsigned VReg; in EmitDbgInstrRef() local
829 AddVRegOp(VReg); in EmitDbgInstrRef()
849 AddVRegOp(VReg); in EmitDbgInstrRef()
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H A DSDNodeDbgValue.h68 return u.VReg; in getVReg()
77 static SDDbgOperand fromVReg(unsigned VReg) { in fromVReg() argument
78 return SDDbgOperand(VReg, VREG); in fromVReg()
110 unsigned VReg; ///< Valid for registers. member
125 u.VReg = VRegOrFrameIdx; in SDDbgOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp296 VReg, MRI, /*LookThroughInstrs*/ false); in getIConstantVRegVal()
297 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && in getIConstantVRegVal()
306 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI); in getIConstantVRegSExtVal()
337 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
340 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
341 if (VReg.isPhysical()) in getConstantVRegValWithLookThrough()
345 VReg = MI->getOperand(1).getReg(); in getConstantVRegValWithLookThrough()
374 return ValueAndVReg{Val, VReg}; in getConstantVRegValWithLookThrough()
435 Reg->VReg}; in getFConstantVRegValWithLookThrough()
440 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal()
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H A DInstructionSelect.cpp262 Register VReg = Register::index2VirtReg(I); in runOnMachineFunction() local
265 if (!MRI.def_empty(VReg)) in runOnMachineFunction()
266 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
267 else if (!MRI.use_empty(VReg)) { in runOnMachineFunction()
268 MI = &*MRI.use_instr_begin(VReg); in runOnMachineFunction()
276 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); in runOnMachineFunction()
283 const LLT Ty = MRI.getType(VReg); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h174 std::optional<APInt> getIConstantVRegVal(Register VReg,
178 std::optional<int64_t> getIConstantVRegSExtVal(Register VReg,
185 Register VReg; member
191 getIConstantVRegValWithLookThrough(Register VReg,
198 Register VReg, const MachineRegisterInfo &MRI,
203 Register VReg; member
209 getFConstantVRegValWithLookThrough(Register VReg,
213 const ConstantFP* getConstantFPVRegVal(Register VReg,
423 std::optional<FPValueAndVReg> getFConstantSplat(Register VReg,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.h248 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) { in addLiveInAttr() argument
249 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); in addLiveInAttr()
254 bool isLiveInSExt(Register VReg) const;
258 bool isLiveInZExt(Register VReg) const;
H A DPPCMachineFunctionInfo.cpp62 bool PPCFunctionInfo::isLiveInSExt(Register VReg) const { in isLiveInSExt()
64 if (LiveIn.first == VReg) in isLiveInSExt()
69 bool PPCFunctionInfo::isLiveInZExt(Register VReg) const { in isLiveInZExt()
71 if (LiveIn.first == VReg) in isLiveInZExt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td145 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
146 VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> {
148 VReg vrclass = regclass;
149 VReg wvrclass = wregclass;
150 VReg f8vrclass = f8regclass;
151 VReg f4vrclass = f4regclass;
152 VReg f2vrclass = f2regclass;
250 VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX,
266 VReg RegClass = M.vrclass;
1314 class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp605 return error(VReg.ID.SourceRange.Start, in parseRegisterInfo()
607 Twine(VReg.ID.Value) + "'"); in parseRegisterInfo()
610 if (StringRef(VReg.Class.Value).equals("_")) { in parseRegisterInfo()
622 VReg.Class.SourceRange.Start, in parseRegisterInfo()
624 VReg.Class.Value + "'"); in parseRegisterInfo()
630 if (!VReg.PreferredRegister.Value.empty()) { in parseRegisterInfo()
632 return error(VReg.Class.SourceRange.Start, in parseRegisterInfo()
646 Register VReg; in parseRegisterInfo() local
652 VReg = Info->VReg; in parseRegisterInfo()
654 RegInfo.addLiveIn(Reg, VReg); in parseRegisterInfo()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp886 Register VReg = MI.getOperand(0).getReg(); in getInstrMapping() local
887 if (!VReg) in getInstrMapping()
889 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
897 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
898 if (!VReg) in getInstrMapping()
900 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
959 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
1030 Register VReg = MI.getOperand(1).getReg(); in getInstrMapping() local
1031 if (!VReg) in getInstrMapping()
1039 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h48 Register VReg) const override;
54 Register VReg) const override;

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