Lines Matching refs:VReg

277     Register VReg = MRI->createVirtualRegister(RC);  in getVR()  local
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
280 return VReg; in getVR()
303 Register VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
327 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
333 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
334 VReg = NewVReg; in AddRegisterOperand()
364 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
385 Register VReg = R->getReg(); in AddOperand() local
397 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) { in AddOperand()
400 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddOperand()
401 VReg = NewVReg; in AddOperand()
407 MIB.addReg(VReg, getImplRegState(Imp)); in AddOperand()
449 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
457 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); in ConstrainForSubReg()
461 return VReg; in ConstrainForSubReg()
469 .addReg(VReg); in ConstrainForSubReg()
611 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
619 NewVReg).addReg(VReg); in EmitCopyToRegClassNode()
808 auto AddVRegOp = [&](unsigned VReg) { in EmitDbgInstrRef() argument
810 /* Reg */ VReg, /* isDef */ false, /* isImp */ false, in EmitDbgInstrRef()
821 unsigned VReg; in EmitDbgInstrRef() local
824 VReg = DbgOperand.getVReg(); in EmitDbgInstrRef()
828 if (!MRI->hasOneDef(VReg)) { in EmitDbgInstrRef()
829 AddVRegOp(VReg); in EmitDbgInstrRef()
833 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
844 VReg = getVR(Op, VRBaseMap); in EmitDbgInstrRef()
848 if (!MRI->hasOneDef(VReg)) { in EmitDbgInstrRef()
849 AddVRegOp(VReg); in EmitDbgInstrRef()
853 DefMI = &*MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
864 AddVRegOp(VReg); in EmitDbgInstrRef()
871 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg) in EmitDbgInstrRef()