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Searched refs:UseMI (Results 1 – 25 of 76) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp25 MachineInstr *UseMI; member
186 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
188 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
204 MachineInstr *MI = Fold.UseMI; in canUseImmWithOpSel()
232 MachineInstr *MI = Fold.UseMI; in tryFoldImmWithOpSel()
356 MachineInstr *MI = Fold.UseMI; in updateOperand()
755 MachineInstr *UseMI, in foldOperand() argument
868 UseMI->removeOperand(UseMI->getOperandNo(Tmp)); in foldOperand()
1362 for (auto &UseMI : in foldInstOperand() local
1384 foldOperand(OpToFold, UseMI, UseMI->getOperandNo(U), FoldList, in foldInstOperand()
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H A DSIOptimizeVGPRLiveRange.cpp215 if (UseMI.getParent() == MBB && !UseMI.isPHI()) in findNonPHIUsesInBlock()
216 Uses.push_back(&UseMI); in findNonPHIUsesInBlock()
305 auto *UseMI = I->getParent(); in collectCandidateRegisters() local
306 auto *UseMBB = UseMI->getParent(); in collectCandidateRegisters()
308 if (!UseMI->isPHI()) in collectCandidateRegisters()
430 auto *UseMI = I->getParent(); in updateLiveRangeInThenRegion() local
521 auto *UseMI = O.getParent(); in optimizeLiveRange() local
522 auto *UseBlock = UseMI->getParent(); in optimizeLiveRange()
525 if (UseMI->isPHI()) in optimizeLiveRange()
527 else if (UseMI->isDebugInstr()) in optimizeLiveRange()
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H A DSIFixSGPRCopies.cpp234 const auto *UseMI = MO.getParent(); in tryChangeVGPRtoSGPRinCopy() local
235 if (UseMI == &MI) in tryChangeVGPRtoSGPRinCopy()
237 if (MO.isDef() || UseMI->getParent() != MI.getParent() || in tryChangeVGPRtoSGPRinCopy()
238 UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END) in tryChangeVGPRtoSGPRinCopy()
242 if (OpIdx >= UseMI->getDesc().getNumOperands() || in tryChangeVGPRtoSGPRinCopy()
243 !TII->isOperandLegal(*UseMI, OpIdx, &Src)) in tryChangeVGPRtoSGPRinCopy()
806 const MachineInstr *UseMI = Use.getParent(); in processPHINode() local
807 AllAGPRUses &= (UseMI->isCopy() && in processPHINode()
810 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
811 if (Visited.insert(UseMI).second) in processPHINode()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp193 MI.getParent() != UseMI.getParent()) in canRemoveAddasl()
199 getBaseWithLongOffset(UseMI) < 0) in canRemoveAddasl()
207 for (auto &Mo : UseMI.operands()) in canRemoveAddasl()
475 Changed |= updateAddUses(AddMI, UseMI); in processAddUses()
496 MachineOperand &BaseOp = UseMI->getOperand(getBaseOpPosition(UseMI)); in updateAddUses()
497 MachineOperand &OffsetOp = UseMI->getOperand(getOffsetOpPosition(UseMI)); in updateAddUses()
718 MIB.add(UseMI->getOperand(0)); in changeAddAsl()
731 MIB.add(UseMI->getOperand(2)); in changeAddAsl()
737 MIB.add(UseMI->getOperand(i)); in changeAddAsl()
739 Deleted.insert(UseMI); in changeAddAsl()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp375 switch (UseMI.getOpcode()) { in foldIntoMemoryOps()
396 if (UseMI.getOperand(1).isFI()) in foldIntoMemoryOps()
399 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
401 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
404 int64_t Offset = UseMI.getOperand(2).getImm(); in foldIntoMemoryOps()
473 for (MachineInstr &UseMI : in foldIntoMemoryOps()
475 if (UseMI.getOpcode() == RISCV::INLINEASM || in foldIntoMemoryOps()
476 UseMI.getOpcode() == RISCV::INLINEASM_BR) { in foldIntoMemoryOps()
479 MachineOperand &MO = UseMI.getOperand(I + 1); in foldIntoMemoryOps()
499 UseMI.removeOperand(2); in foldIntoMemoryOps()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp209 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
221 if (UseMI && UseMI != MI) in foldAsLoad()
226 UseMI = MI; in foldAsLoad()
229 if (!DefMI || !UseMI) in foldAsLoad()
235 LIS.getInstructionIndex(*UseMI))) in foldAsLoad()
245 << " into single use: " << *UseMI); in foldAsLoad()
248 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second) in foldAsLoad()
255 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI); in foldAsLoad()
257 if (UseMI->shouldUpdateCallSiteInfo()) in foldAsLoad()
258 UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI); in foldAsLoad()
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H A DMachineTraceMetrics.cpp673 if (UseMI.isDebugInstr()) in getDataDeps()
697 static void getPHIDeps(const MachineInstr &UseMI, in getPHIDeps() argument
704 assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI"); in getPHIDeps()
758 LRU.MI = UseMI; in updatePhysDepsDownwards()
799 if (UseMI.isPHI()) in updateDepth()
800 getPHIDeps(UseMI, Deps, TBI.Pred, MTM.MRI); in updateDepth()
801 else if (getDataDeps(UseMI, Deps, MTM.MRI)) in updateDepth()
821 InstrCycles &MICycles = Cycles[&UseMI]; in updateDepth()
896 for (const auto &UseMI : *MBB) { in computeInstrDepths()
897 updateDepth(TBI, UseMI, RegUnits); in computeInstrDepths()
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H A DTargetSchedule.cpp175 const MachineInstr *UseMI, unsigned UseOperIdx) const { in computeOperandLatency() argument
185 if (UseMI) { in computeOperandLatency()
187 *UseMI, UseOperIdx); in computeOperandLatency()
209 if (!UseMI) in computeOperandLatency()
213 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
216 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency()
H A DMachineLICM.cpp998 if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI)) in isCopyFeedingInvariantStore()
1063 if (UseMI.isPHI()) { in HasLoopPHIUse()
1066 if (CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1071 if (isExitBlock(CurLoop, UseMI.getParent())) in HasLoopPHIUse()
1076 if (UseMI.isCopy() && CurLoop->contains(&UseMI)) in HasLoopPHIUse()
1077 Work.push_back(&UseMI); in HasLoopPHIUse()
1093 if (UseMI.isCopyLike()) in HasHighOperandLatency()
1095 if (!CurLoop->contains(UseMI.getParent())) in HasHighOperandLatency()
1098 const MachineOperand &MO = UseMI.getOperand(i); in HasHighOperandLatency()
1272 [&CurLoop](MachineInstr &UseMI) { in IsProfitableToHoist() argument
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H A DDetectDeadLanes.cpp339 const MachineInstr &UseMI = *MO.getParent(); in determineInitialUsedLanes() local
340 if (UseMI.isKill()) in determineInitialUsedLanes()
344 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
345 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
346 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
353 if (lowersToCopies(UseMI)) { in determineInitialUsedLanes()
355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
357 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI); in determineInitialUsedLanes()
H A DOptimizePHIs.cpp155 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
156 if (!UseMI.isPHI() || !IsDeadPHICycle(&UseMI, PHIsInCycle)) in IsDeadPHICycle()
H A DMachineSSAUpdater.cpp235 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
237 if (UseMI->isPHI()) { in RewriteUse()
238 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
241 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
H A DTailDuplicator.cpp218 MachineInstr *UseMI = UseMO.getParent(); in tailDuplicateAndUpdate() local
223 if (UseMI->isDebugValue()) { in tailDuplicateAndUpdate()
227 if (UseMI->getParent() == DefBB && !UseMI->isPHI()) in tailDuplicateAndUpdate()
232 MachineInstr *UseMI = UseMO->getParent(); in tailDuplicateAndUpdate() local
234 SSAUpdate.GetValueInMiddleOfBlock(UseMI->getParent(), true)); in tailDuplicateAndUpdate()
299 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { in isDefLiveOut()
300 if (UseMI.isDebugValue()) in isDefLiveOut()
302 if (UseMI.getParent() != BB) in isDefLiveOut()
H A DPeepholeOptimizer.cpp547 MachineInstr *UseMI = UseMO.getParent(); in INITIALIZE_PASS_DEPENDENCY() local
548 if (UseMI == &MI) in INITIALIZE_PASS_DEPENDENCY()
551 if (UseMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
577 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
580 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
583 if (!LocalMIs.count(UseMI)) in INITIALIZE_PASS_DEPENDENCY()
620 MachineInstr *UseMI = UseMO->getParent(); in INITIALIZE_PASS_DEPENDENCY() local
621 MachineBasicBlock *UseMBB = UseMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
646 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
649 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(), in INITIALIZE_PASS_DEPENDENCY()
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H A DRegisterScavenging.cpp225 MachineBasicBlock::iterator &UseMI) { in spill() argument
270 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) { in spill()
287 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register()); in spill()
288 II = std::prev(UseMI); in spill()
304 MachineBasicBlock::iterator UseMI; in scavengeRegisterBackwards() local
H A DRegisterCoalescer.cpp883 MachineInstr *UseMI = MO.getParent(); in removeCopyByCommutingDef() local
929 if (UseMI->isDebugInstr()) { in removeCopyByCommutingDef()
946 if (UseMI == CopyMI) in removeCopyByCommutingDef()
948 if (!UseMI->isCopy()) in removeCopyByCommutingDef()
951 UseMI->getOperand(0).getSubReg()) in removeCopyByCommutingDef()
972 deleteInstr(UseMI); in removeCopyByCommutingDef()
1637 if (UseMI->isDebugInstr()) { in reMaterializeTrivialDef()
1644 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI); in reMaterializeTrivialDef()
1838 MachineInstr *UseMI = &*(I++); in updateRegDefsUses() local
1900 if (!UseMI->isDebugInstr()) in updateRegDefsUses()
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H A DModuloSchedule.cpp82 MachineInstr *UseMI = UseOp.getParent(); in expand() local
83 int UseStage = Schedule.getStage(UseMI); in expand()
1147 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr() local
1148 if (UseMI->getParent() != BB) in rewriteScheduledInstr()
1150 if (UseMI->isPHI()) { in rewriteScheduledInstr()
1153 if (getLoopPhiReg(*UseMI, BB) != OldReg) in rewriteScheduledInstr()
1188 BuildMI(*BB, UseMI, UseMI->getDebugLoc(), TII->get(TargetOpcode::COPY), in rewriteScheduledInstr()
1621 assert(UseMI.isPHI()); in filterInstructions()
1624 Subs.emplace_back(&UseMI, Reg); in filterInstructions()
1935 assert(UseMI.isPHI()); in rewriteUsesOf()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp232 if (UseMI->isCopy()) in reload()
233 TileReg = UseMI->getOperand(0).getReg(); in reload()
242 MachineInstr *NewMI = BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), in reload()
246 BuildMI(*UseMI->getParent(), UseMI, DebugLoc(), TII->get(Opc), TileReg) in reload()
256 if (UseMI->isCopy()) { in reload()
257 UseMI->eraseFromParent(); in reload()
260 for (auto &MO : UseMI->operands()) { in reload()
626 if (UseMI.getParent() == &MBB) { in configBasicBlock()
631 reload(UseMI.getIterator(), TileReg, RowMO, ColMO); in configBasicBlock()
635 if (!UseMI.isPHI()) in configBasicBlock()
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H A DX86SpeculativeLoadHardening.cpp1780 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) { in sinkPostLoadHardenedInst()
1783 if (HardenedInstrs.count(&UseMI)) { in sinkPostLoadHardenedInst()
1784 if (!X86InstrInfo::isDataInvariantLoad(UseMI) || isEFLAGSDefLive(UseMI)) { in sinkPostLoadHardenedInst()
1788 assert(X86InstrInfo::isDataInvariant(UseMI) && in sinkPostLoadHardenedInst()
1800 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
1802 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
1818 if (!X86InstrInfo::isDataInvariant(UseMI) || UseMI.getParent() != MI.getParent() || in sinkPostLoadHardenedInst()
1819 isEFLAGSDefLive(UseMI)) in sinkPostLoadHardenedInst()
1824 if (UseMI.getDesc().getNumDefs() > 1) in sinkPostLoadHardenedInst()
1830 Register UseDefReg = UseMI.getOperand(0).getReg(); in sinkPostLoadHardenedInst()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp128 MachineInstr &UseMI = *MOUse.getParent(); in localizeInterBlock() local
129 if (MRI->hasOneUse(Reg) && !UseMI.isPHI()) in localizeInterBlock()
130 InsertMBB->insert(UseMI, LocalizedMI); in localizeInterBlock()
165 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) { in localizeIntraBlock()
166 if (!UseMI.isPHI()) in localizeIntraBlock()
167 Users.insert(&UseMI); in localizeIntraBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg() local
123 if (UseMI->getParent() != MBB) in getDefReg()
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
127 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg); in getDefReg()
131 if (UseMI->getParent() != MBB) in getDefReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp679 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
680 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
692 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
701 Register SwapDefReg = UseMI.getOperand(0).getReg(); in recordUnoptimizableWebs()
713 LLVM_DEBUG(UseMI.dump()); in recordUnoptimizableWebs()
745 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
746 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs()
787 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
788 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval()
792 LLVM_DEBUG(UseMI.dump()); in markSwapsForRemoval()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp58 MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, in saveScavengerRegister() argument
63 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); in saveScavengerRegister()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp578 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
639 LLVM_DEBUG(UseMI.dump()); in FoldImmediate()
661 switch (UseMI.getOpcode()) { in FoldImmediate()
708 if (UseMI.getOperand(1).getReg() == Reg) { in FoldImmediate()
711 assert(UseMI.getOperand(2).getReg() == Reg); in FoldImmediate()
725 if (UseMI.getOperand(1).getReg() == Reg) { in FoldImmediate()
732 assert(UseMI.getOperand(2).getReg() == Reg); in FoldImmediate()
745 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
747 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); in FoldImmediate()
749 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); in FoldImmediate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp215 [&](const MachineInstr &UseMI) { return onlyUsesFP(UseMI, MRI, TRI); }); in anyUseOnlyUseFP() argument
364 [&](const MachineInstr &UseMI) { in getInstrMapping() argument
365 return onlyUsesFP(UseMI, MRI, TRI); in getInstrMapping()

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