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Searched refs:Tmp2 (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
82 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
104 Value* Tmp2 = Builder.CreateLShr(V, in LowerBSWAP() local
130 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp374 SDValue Tmp2 = Val; in PerformInsertVectorEltInMemory() local
3559 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred); in ExpandNode()
3923 Tmp2 = DAG.getNode( in ExpandNode()
3998 Tmp2.getOperand(0), Tmp2.getOperand(1), in ExpandNode()
4003 (Tmp2.getOpcode() == ISD::AND && isOneConstant(Tmp2.getOperand(1)))) in ExpandNode()
4004 Tmp3 = Tmp2; in ExpandNode()
4006 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, in ExpandNode()
4172 DAG, getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, in ExpandNode()
5111 Tmp2 = DAG.getNode( in PromoteNode()
5339 {Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)}); in PromoteNode()
[all …]
H A DTargetLowering.cpp9055 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); in expandBSWAP()
9075 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, in expandBSWAP()
9081 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); in expandBSWAP()
9118 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2, in expandVPBSWAP()
9123 Tmp2 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp2, Tmp1, Mask, EVL); in expandVPBSWAP()
9150 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2, in expandVPBSWAP()
9211 Tmp2 = in expandBITREVERSE()
9214 Tmp2 = in expandBITREVERSE()
9253 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2, in expandVPBITREVERSE()
9264 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp2, in expandVPBITREVERSE()
[all …]
H A DSelectionDAG.cpp4278 unsigned Tmp, Tmp2; in ComputeNumSignBits() local
4332 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1); in ComputeNumSignBits()
4394 Tmp2 = VTBits; in ComputeNumSignBits()
4402 Tmp2 = std::min(Tmp2, Tmp - SubOffset); in ComputeNumSignBits()
4404 return Tmp2; in ComputeNumSignBits()
4421 return std::max(Tmp, Tmp2); in ComputeNumSignBits()
4466 return std::min(Tmp, Tmp2); in ComputeNumSignBits()
4471 return std::min(Tmp, Tmp2); in ComputeNumSignBits()
4498 return std::min(Tmp, Tmp2); in ComputeNumSignBits()
4506 return std::min(Tmp, Tmp2); in ComputeNumSignBits()
[all …]
H A DLegalizeFloatTypes.cpp1948 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
1952 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo, in FloatExpandSetCCOperands()
1954 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
1955 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1960 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
1962 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
1963 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4128 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4164 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4197 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4490 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
4876 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in tryVPTESTM() local
5379 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5432 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5519 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5653 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5661 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; in Select() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp123 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); in generateSignedDivisionCode() local
124 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp); in generateSignedDivisionCode()
252 Value *Tmp2 = Builder.CreateSub(MSB, SR); in generateUnsignedDivisionCode() local
253 Value *Q = Builder.CreateShl(Dividend, Tmp2); in generateUnsignedDivisionCode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2032 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareMBB() local
2044 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2049 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2060 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2064 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2110 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2130 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2152 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2525 Register Tmp2 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2541 .addReg(Tmp2, getKillRegState(true)) in emitSjLjDispatchBlock()
[all …]
/freebsd-14.2/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp49 ExplodedNodeSet Tmp2; in VisitBinaryOperator() local
74 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal), in VisitBinaryOperator()
80 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx); in VisitBinaryOperator()
185 evalStore(Tmp2, B, LHS, N, state, location, LHSVal); in VisitBinaryOperator()
190 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this); in VisitBinaryOperator()
H A DCheckerManager.cpp123 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
131 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1943 SmallVector<MachineOperand,1> Tmp2; in createPreheaderForLoop() local
1950 Tmp2.clear(); in createPreheaderForLoop()
1951 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); in createPreheaderForLoop()
1954 if (TB != Header && (Tmp2.empty() || FB != Header)) in createPreheaderForLoop()
1963 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp689 auto *Tmp2 = in splitMemRef() local
691 HighI->addMemOperand(MF, Tmp2); in splitMemRef()
H A DHexagonISelLoweringHVX.cpp2465 SDValue Tmp2 = DAG.getNode(ShRight, dl, IntTy, Tmp0, AmtM1); in emitHvxShiftRightRnd() local
2466 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, IntTy, Tmp2, Rup); in emitHvxShiftRightRnd()
2468 SDValue Eq = DAG.getSetCC(dl, PredTy, Tmp1, Tmp2, ISD::SETEQ); in emitHvxShiftRightRnd()
2470 SDValue Tmp4 = DAG.getNode(ShRight, dl, IntTy, {Tmp2, One}); in emitHvxShiftRightRnd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp3303 unsigned Tmp, Tmp2; in ComputeNumSignBitsImpl() local
3388 Tmp2 = ShAmt->getZExtValue(); in ComputeNumSignBitsImpl()
3389 return Tmp - Tmp2; in ComputeNumSignBitsImpl()
3400 FirstAnswer = std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
3418 return std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
3445 if (Tmp2 == 1) break; in ComputeNumSignBitsImpl()
3446 return std::min(Tmp, Tmp2) - 1; in ComputeNumSignBitsImpl()
3450 if (Tmp2 == 1) break; in ComputeNumSignBitsImpl()
3466 return Tmp2; in ComputeNumSignBitsImpl()
3475 return std::min(Tmp, Tmp2) - 1; in ComputeNumSignBitsImpl()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2457 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts() local
2458 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2517 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts() local
2518 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2751 SDValue Tmp2 = Node->getOperand(1); in LowerVAARG() local
2755 Tmp1, Tmp2, MachinePointerInfo(V)); in LowerVAARG()
2774 Tmp1 = DAG.getStore(VAListLoad.getValue(1), DL, Tmp1, Tmp2, in LowerVAARG()
3015 SDValue Tmp2 = ST->getBasePtr(); in LowerSTOREi1() local
3020 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2404 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC() local
2406 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2423 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN() local
2434 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFROUNDEVEN()
5779 unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1); in ComputeNumSignBitsForTargetNode() local
5780 if (Tmp2 == 1) in ComputeNumSignBitsForTargetNode()
5791 return std::min(Tmp0, std::min(Tmp1, Tmp2)); in ComputeNumSignBitsForTargetNode()
5819 unsigned Tmp2 = Analysis.computeNumSignBits(Src2, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
5820 if (Tmp2 == 1) in computeNumSignBitsForTargetInstr()
5828 return std::min(Tmp0, std::min(Tmp1, Tmp2)); in computeNumSignBitsForTargetInstr()
H A DAMDGPULegalizerInfo.cpp2340 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFroundeven() local
2346 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFroundeven()
4752 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); in legalizeFastUnsafeFDIV64() local
4754 B.buildFMA(Res, Tmp2, R, Ret); in legalizeFastUnsafeFDIV64()
H A DSIInstrInfo.cpp711 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, in indirectCopyToAGPR() local
714 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
716 Tmp = Tmp2; in indirectCopyToAGPR()
H A DSIISelLowering.cpp3874 SDValue Tmp2 = Op.getValue(1); in lowerDYNAMIC_STACKALLOCImpl() local
3884 SDValue Size = Tmp2.getOperand(1); in lowerDYNAMIC_STACKALLOCImpl()
3907 Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl); in lowerDYNAMIC_STACKALLOCImpl()
3909 return DAG.getMergeValues({Tmp1, Tmp2}, dl); in lowerDYNAMIC_STACKALLOCImpl()
10331 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64() local
10332 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret); in lowerFastUnsafeFDIV64()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1025 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d in EmitBinDiv() local
1026 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6259 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6261 SDValue(Tmp2, 0))); in Select()
6273 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6275 SDValue(Tmp2, 0))); in Select()
H A DPPCISelLowering.cpp8991 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS() local
8993 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
9020 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS() local
9022 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
9048 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRA_PARTS() local
9050 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1877 SDValue Tmp1, Tmp2; in ReplaceNodeResults() local
1878 TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG); in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6482 SDValue Tmp2 = Op.getOperand(1); in LowerOperation() local
6492 DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags()); in LowerOperation()
10253 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc() local
10256 Tmp1.getValue(1), Tmp2.getValue(1)); in lowerVectorStrictFSetcc()
10258 if (Tmp1 != Tmp2) in lowerVectorStrictFSetcc()
10259 Tmp1 = DAG.getNode(ISD::AND, DL, VT, Tmp1, Tmp2); in lowerVectorStrictFSetcc()
16422 unsigned Tmp2 = in ComputeNumSignBitsForTargetNode() local
16424 return std::min(Tmp, Tmp2); in ComputeNumSignBitsForTargetNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp4183 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32); in Select() local
4184 SDValue Ops[] = { N1, Tmp2, N3, Chain, InGlue }; in Select()

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