| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 80 Register SuperReg; member
140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
202 RS->setRegUsed(SuperReg); in prepare()
1776 ? SB.SuperReg in spillSGPR()
1830 ? SB.SuperReg in spillSGPR()
1870 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in spillSGPR()
1892 ? SB.SuperReg in restoreSGPR()
1925 ? SB.SuperReg in restoreSGPR()
1950 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in restoreSGPR()
1972 ? SB.SuperReg in spillEmergencySGPR()
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| H A D | SIFrameLowering.cpp | 233 Register SuperReg; member in llvm::PrologEpilogSGPRSpillBuilder
255 ? SuperReg in saveToMemory()
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
276 ? SuperReg in saveToVGPRLane()
288 .addReg(SuperReg) in copyToScratchSGPR()
303 ? SuperReg in restoreFromMemory()
322 ? SuperReg in restoreFromVGPRLane()
331 BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), SuperReg) in copyFromScratchSGPR()
347 SuperReg(Reg), SI(SI), LiveUnits(LiveUnits), DL(DL), in PrologEpilogSGPRSpillBuilder()
349 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in PrologEpilogSGPRSpillBuilder()
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| H A D | SIInstrInfo.h | 109 const MachineOperand &SuperReg,
115 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.cpp | 5526 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5532 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) { in buildExtractSubReg()
5534 .addReg(SuperReg.getReg(), 0, SubIdx); in buildExtractSubReg()
5545 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg()); in buildExtractSubReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 536 unsigned SuperReg, unsigned AntiDepGroupIndex, RenameOrderType &RenameOrder, in FindSuitableFreeRegisters() argument
577 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
578 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
593 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
607 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
629 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
639 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
642 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| H A D | AggressiveAntiDepBreaker.h | 179 bool FindSuitableFreeRegisters(unsigned SuperReg,
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| H A D | CriticalAntiDepBreaker.cpp | 243 for (MCPhysReg SuperReg : TRI->superregs(Reg)) { in PrescanInstruction() local
244 KeepRegs.set(SuperReg); in PrescanInstruction()
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| H A D | PrologEpilogInserter.cpp | 460 for (const MCPhysReg &SuperReg : RegInfo->superregs(Reg)) { in assignCalleeSavedSpillSlots() local
463 if (SavedRegs.test(SuperReg) && CSMask.test(SuperReg)) { in assignCalleeSavedSpillSlots()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1576 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1612 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1614 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1718 SDValue SuperReg = SDValue(WhilePair, 0); in SelectPExtPair() local
1734 SDValue SuperReg = SDValue(WhilePair, 0); in SelectWhilePair() local
1819 SDValue SuperReg = SDValue(Load, 0); in SelectPredicatedLoad() local
1854 SDValue SuperReg = SDValue(Load, 0); in SelectContiguousMultiVectorLoad() local
2005 SDValue SuperReg = SDValue(Res, 0); in SelectUnaryMultiIntrinsic() local
2153 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
2201 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2237 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2244 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2486 SDValue SuperReg; in SelectVLDSTLane() local
2491 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2493 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2500 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2502 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2504 Ops.push_back(SuperReg); in SelectVLDSTLane()
2520 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2527 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 369 SDValue SuperReg = SDValue(Load, 0); in selectVLSEG() local
373 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
410 SDValue SuperReg = SDValue(Load, 0); in selectVLSEGFF() local
414 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
462 SDValue SuperReg = SDValue(Load, 0); in selectVLXSEG() local
466 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1672 MCRegister SuperReg = in copyPhysReg() local
1675 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1678 DestReg = SuperReg; in copyPhysReg()
1681 MCRegister SuperReg = in copyPhysReg() local
1684 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1687 SrcReg = SuperReg; in copyPhysReg()
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