80   Register SuperReg;  member
121       : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),  in SGPRSpillBuilder()
125     const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);  in SGPRSpillBuilder()
139     assert(SuperReg != AMDGPU::M0 && "m0 should never spill");  in SGPRSpillBuilder()
140     assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in SGPRSpillBuilder()
141            SuperReg != AMDGPU::EXEC && "exec should never spill");  in SGPRSpillBuilder()
202     RS->setRegUsed(SuperReg);  in prepare()
1765   assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&  in spillSGPR()
1766                          SB.SuperReg != SB.MFI.getFrameOffsetReg()));  in spillSGPR()
1776               ? SB.SuperReg  in spillSGPR()
1777               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1802         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillSGPR()
1806         MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);  in spillSGPR()
1830                 ? SB.SuperReg  in spillSGPR()
1831                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1855           WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillSGPR()
1870     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in spillSGPR()
1892               ? SB.SuperReg  in restoreSGPR()
1893               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1901         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1925                 ? SB.SuperReg  in restoreSGPR()
1926                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1934           MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1950     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in restoreSGPR()
1972               ? SB.SuperReg  in spillEmergencySGPR()
1973               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
1989         WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillEmergencySGPR()
2007               ? SB.SuperReg  in spillEmergencySGPR()
2008               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
2015         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillEmergencySGPR()