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Searched refs:Subtarget (Results 1 – 25 of 305) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrPredicates.td55 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
57 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
59 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
61 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
64 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
66 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
71 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
76 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
77 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
89 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
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H A DX86ISelLoweringCall.cpp123 !Subtarget.hasX87()) in getRegisterTypeForCallingConv()
157 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) { in getNumRegistersForCallingConv()
187 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() && in getVectorTypeBreakdownForCallingConv()
287 if (Op.size() >= 64 && Subtarget.hasAVX512() && Subtarget.hasEVEX512() && in getOptimalMemOpType()
301 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128)) in getOptimalMemOpType()
305 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
401 if (Subtarget.hasAVX512() && Subtarget.hasEVEX512()) in allowsMemoryAccess()
901 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ? in LowerReturn()
1394 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() && in LowerMemArgument()
1469 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget), in VarArgsLoweringHelper()
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H A DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
122 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
157 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
179 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
184 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
197 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
217 if (Subtarget.hasERMSB()) in emitConstantSizeRepmov()
220 assert(!Subtarget.hasERMSB() && "No efficient RepMovs"); in emitConstantSizeRepmov()
231 emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitConstantSizeRepmov()
276 const X86Subtarget &Subtarget = in EmitTargetCodeForMemcpy() local
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H A DX86ISelLowering.cpp115 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
354 if (!Subtarget.useSoftFloat() && Subtarget.hasX87()) { in X86TargetLowering()
817 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
6495 if (Subtarget.hasSSE3() && !Subtarget.hasXOP() && in LowerBuildVectorv4x32()
8397 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
8432 if (Subtarget.hasVLX() && Subtarget.hasVBMI()) in createVariablePermute()
8466 if (Subtarget.hasVLX() && Subtarget.hasBWI()) in createVariablePermute()
10589 if (Subtarget.hasBWI() && Subtarget.hasVLX()) { in lowerShuffleAsBlend()
19141 if (Subtarget.hasDQI() && Subtarget.hasVLX() && in isLegalConversion()
30150 (Subtarget.hasSSE1() || Subtarget.hasX87())) in shouldExpandAtomicStoreInIR()
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H A DX86FastISel.cpp50 const X86Subtarget *Subtarget; member in __anond0edf0320111::X86FastISel
1929 if (!Subtarget->is64Bit()) in X86SelectDivRem()
2025 if (!Subtarget->canUseCMOV()) in X86FastEmitCMoveSelect()
2196 if (Subtarget->hasAVX512()) { in X86FastEmitSSESelect()
2589 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) in fastLowerIntrinsicCall()
2788 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2969 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3034 if (!Subtarget->hasCRC32()) in fastLowerIntrinsicCall()
3102 if (!Subtarget->is64Bit()) in fastLowerArguments()
3188 if (Subtarget->is64Bit()) in computeBytesPoppedByCalleeForSRet()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
53 def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">,
190 …def UseMovtInPic : Predicate<"Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt(…
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H A DARMMachineFunctionInfo.cpp29 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement() argument
30 if (!Subtarget->isMClass() || !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement()
75 const ARMSubtarget *Subtarget) in ARMFunctionInfo() argument
76 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in ARMFunctionInfo()
79 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in ARMFunctionInfo()
80 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in ARMFunctionInfo()
H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
141 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
163 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
172 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
176 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
191 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
202 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
220 if (NumMEMCPYs > 1 && Subtarget.hasMinSize()) { in EmitTargetCodeForMemcpy()
299 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemset() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
130 if (Subtarget.isABI_N64()) in getCallPreservedMask()
133 if (Subtarget.isABI_N32()) in getCallPreservedMask()
136 if (Subtarget.isFP64bit()) in getCallPreservedMask()
139 if (Subtarget.isFPXX()) in getCallPreservedMask()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td22 // Subtarget Features (device properties)
862 // Subtarget Features (options and debugging)
1658 Predicate<"!Subtarget->hasGFX90AInsts() &&"
1715 Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1719 Predicate<"Subtarget->hasGFX90AInsts()">,
1723 Predicate<"!Subtarget->hasGFX90AInsts()">,
1733 Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1737 Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1741 Predicate<"Subtarget->hasGFX940Insts()">,
1881 Predicate<"Subtarget->hasSDWA()">,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp52 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
75 if (!Subtarget) in getCPUSuffix()
78 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
80 if (Subtarget->hasP9Vector()) in getCPUSuffix()
82 if (Subtarget->hasP8Vector()) in getCPUSuffix()
84 if (Subtarget->isAIXABI()) in getCPUSuffix()
97 StringRef Suffix = getCPUSuffix(Subtarget); in createMASSVFuncName()
144 std::string MASSVEntryName = createMASSVFuncName(Func, Subtarget); in lowerMASSVCall()
161 const PPCSubtarget *Subtarget; in runOnModule() local
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H A DPPCRegisterInfo.cpp190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
256 if (Subtarget.isAIXABI()) { in getCalleeSavedRegs()
267 if (Subtarget.hasAltivec()) in getCalleeSavedRegs()
282 if (Subtarget.hasVSX()) { in getCallPreservedMask()
297 if (Subtarget.isAIXABI()) { in getCallPreservedMask()
384 if (Subtarget.isSVR4ABI()) { in getReservedRegs()
398 if (Subtarget.isAIXABI()) in getReservedRegs()
424 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() && in getReservedRegs()
544 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI()) in isCallerPreservedPhysReg()
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H A DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
243 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
540 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in twoUniqueScratchRegsRequired()
569 if (!Subtarget.isELFv2ABI() || !Subtarget.isPPC64()) in stackUpdateCanBeMoved()
1265 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in inlineStackProbe()
1572 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); in emitEpilogue()
2053 Subtarget.isPPC64() ? 8 : Subtarget.isAIXABI() ? 4 : -4; in determineCalleeSaves()
2332 if (Subtarget.hasSPE()) { in assignCalleeSavedSpillSlots()
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H A DPPCISelLowering.cpp695 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
1649 if (!Subtarget.isPPC64() || !Subtarget.hasVSX()) in shallExtractConstSplatVectorElementToStore()
3237 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3244 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3261 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3903 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
5770 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in isEligibleForTCO()
8684 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8832 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9457 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td143 : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
321 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
335 def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
354 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
355 "Subtarget->hasStdExtZce()">,
416 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
434 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
459 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
597 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
655 def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb…
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H A DRISCVISelLowering.cpp271 if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb()) in RISCVTargetLowering()
292 if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) { in RISCVTargetLowering()
330 if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) { in RISCVTargetLowering()
387 if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb() || in RISCVTargetLowering()
544 if (Subtarget.hasStdExtFOrZfinx() && Subtarget.is64Bit()) in RISCVTargetLowering()
1389 if (Subtarget.hasStdExtZbs() && Subtarget.is64Bit()) in RISCVTargetLowering()
1826 if (!Subtarget.hasStdExtZbs() && !Subtarget.hasVendorXTHeadBs()) in isMaskAndCmp0FoldingBeneficial()
1841 return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) && in hasAndNotCompare()
11600 !(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb())) in ReplaceNodeResults()
11625 Subtarget.is64Bit() && Subtarget.hasStdExtM() && in ReplaceNodeResults()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp162 const RISCVSubtarget &Subtarget; member
278 const RISCVSubtarget &Subtarget; member
312 return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true; in isLegalElementTypeForRVV()
317 return Subtarget.hasVInstructionsI64(); in isLegalElementTypeForRVV()
319 return Subtarget.hasVInstructionsF16(); in isLegalElementTypeForRVV()
321 return Subtarget.hasVInstructionsBF16(); in isLegalElementTypeForRVV()
323 return Subtarget.hasVInstructionsF32(); in isLegalElementTypeForRVV()
325 return Subtarget.hasVInstructionsF64(); in isLegalElementTypeForRVV()
389 const RISCVSubtarget &Subtarget = in lowerReturnVal() local
503 const RISCVSubtarget &Subtarget = in lowerFormalArguments() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp40 const AArch64Subtarget *Subtarget = nullptr; member in __anon6e480db00111::AArch64PointerAuth
70 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in BuildPACM()
83 if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR()) in BuildPACM()
113 if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in signLR()
120 BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR()
214 MachinePointerInfo PointerInfo(Subtarget.getAddressCheckPSV()); in createCheckMemOperand()
230 const AArch64InstrInfo *TII = Subtarget.getInstrInfo(); in checkAuthenticatedRegister()
243 .addMemOperand(createCheckMemOperand(MF, Subtarget)); in checkAuthenticatedRegister()
365 Subtarget = &MF.getSubtarget<AArch64Subtarget>(); in runOnMachineFunction()
366 TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand()
46 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_LO8_GS in lowerSymbolOperand()
55 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_HI8_GS in lowerSymbolOperand()
70 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local
91 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction()
95 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction()
105 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction()
109 Subtarget); in lowerInstruction()
113 Subtarget); in lowerInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonPasses.cpp40 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
41 if (!Subtarget->insertNOPLoad()) in runOnMachineFunction()
44 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
79 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
80 if (!Subtarget->detectRoundChange()) in runOnMachineFunction()
129 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
130 if (!Subtarget->fixAllFDIVSQRT()) in runOnMachineFunction()
133 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DSparcRegisterInfo.cpp54 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
65 if (!Subtarget.is64Bit()) in getReservedRegs()
80 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
88 if (!Subtarget.isV9()) { in getReservedRegs()
117 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
183 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
192 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
194 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
206 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp28 const CSKYSubtarget *Subtarget; member in __anon046c90470111::CSKYDAGToDAGISel
38 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
85 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in INITIALIZE_PASS()
283 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
308 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
314 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
319 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry()
327 static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget, in InvertCarryFlag() argument
351 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectSubCarry()
357 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectSubCarry()
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H A DCSKY.td37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
107 def HasSTM : Predicate<"Subtarget->hasSTM()">,
119 def HasDSP : Predicate<"Subtarget->hasDSP()">,
169 def HasJAVA : Predicate<"Subtarget->hasJAVA()">,
181 def HasNVIC : Predicate<"Subtarget->hasNVIC()">,
255 def UseCCRT : Predicate<"Subtarget->useCCRT()">,
268 def iHasE1 : Predicate<"Subtarget->hasE1()">,
275 def iHasE2 : Predicate<"Subtarget->hasE2()">,
281 def iHas2E3 : Predicate<"Subtarget->has2E3()">,
287 def iHasMP : Predicate<"Subtarget->hasMP()">,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
227 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td24 : Predicate<"Subtarget->is64Bit()">,
28 : Predicate<"!Subtarget->is64Bit()">,
39 def HasBasicF : Predicate<"Subtarget->hasBasicF()">;
46 def HasBasicD : Predicate<"Subtarget->hasBasicD()">;
52 def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;
59 def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;
65 def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;
71 def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;
78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
87 : Predicate<"Subtarget->hasLaGlobalWithAbs()">,
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