Lines Matching refs:Subtarget
162 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
169 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
178 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
203 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
233 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
249 if (Subtarget.useCRBits()) { in PPCTargetLowering()
252 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
326 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
361 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
366 if (Subtarget.hasVSX()) { in PPCTargetLowering()
371 if (Subtarget.hasFSQRT()) { in PPCTargetLowering()
376 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
417 if (Subtarget.hasSPE()) { in PPCTargetLowering()
425 if (Subtarget.hasSPE()) in PPCTargetLowering()
431 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
432 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
433 Subtarget.hasFRE())) in PPCTargetLowering()
436 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
437 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
438 Subtarget.hasFRES())) in PPCTargetLowering()
441 if (Subtarget.hasFCPSGN()) { in PPCTargetLowering()
449 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
463 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
470 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand); in PPCTargetLowering()
474 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
482 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) { in PPCTargetLowering()
494 if (!Subtarget.useCRBits()) { in PPCTargetLowering()
507 if (!Subtarget.useCRBits()) in PPCTargetLowering()
510 if (Subtarget.hasFPU()) { in PPCTargetLowering()
521 if (!Subtarget.useCRBits()) in PPCTargetLowering()
526 if (Subtarget.hasSPE()) { in PPCTargetLowering()
550 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
607 if (Subtarget.is64BitELFABI()) { in PPCTargetLowering()
618 } else if (Subtarget.is32BitELFABI()) { in PPCTargetLowering()
626 if (Subtarget.is32BitELFABI()) in PPCTargetLowering()
658 if (Subtarget.hasSPE()) { in PPCTargetLowering()
680 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
695 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
701 if (Subtarget.hasSPE()) { in PPCTargetLowering()
711 if (Subtarget.hasFPCVT()) { in PPCTargetLowering()
712 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
733 if (Subtarget.use64BitRegs()) { in PPCTargetLowering()
751 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
758 if (Subtarget.hasVSX()) { in PPCTargetLowering()
765 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
794 if (Subtarget.hasVSX()) { in PPCTargetLowering()
800 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
810 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
884 if (!Subtarget.hasP8Vector()) { in PPCTargetLowering()
908 Subtarget.useCRBits() ? Legal : Expand); in PPCTargetLowering()
926 if (Subtarget.hasAltivec()) in PPCTargetLowering()
930 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
941 if (Subtarget.hasVSX()) { in PPCTargetLowering()
947 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
952 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
990 if (Subtarget.hasVSX()) { in PPCTargetLowering()
993 if (Subtarget.hasP8Vector()) { in PPCTargetLowering()
997 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1048 if (Subtarget.hasP8Vector()) in PPCTargetLowering()
1057 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1084 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1187 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
1192 if (Subtarget.hasP9Vector()) { in PPCTargetLowering()
1197 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1256 } else if (Subtarget.hasVSX()) { in PPCTargetLowering()
1300 if (Subtarget.hasP9Altivec()) { in PPCTargetLowering()
1301 if (Subtarget.isISA3_1()) { in PPCTargetLowering()
1324 if (Subtarget.hasP10Vector()) { in PPCTargetLowering()
1329 if (Subtarget.pairedVectorMemops()) { in PPCTargetLowering()
1334 if (Subtarget.hasMMA()) { in PPCTargetLowering()
1335 if (Subtarget.isISAFuture()) in PPCTargetLowering()
1344 if (Subtarget.has64BitSupport()) in PPCTargetLowering()
1347 if (Subtarget.isISA3_1()) in PPCTargetLowering()
1365 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
1392 if (Subtarget.hasFPCVT()) in PPCTargetLowering()
1395 if (Subtarget.useCRBits()) in PPCTargetLowering()
1404 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1434 if (Subtarget.isAIXABI()) { in PPCTargetLowering()
1443 if (Subtarget.useCRBits()) { in PPCTargetLowering()
1456 switch (Subtarget.getCPUDirective()) { in PPCTargetLowering()
1478 if (Subtarget.enableMachineScheduler()) in PPCTargetLowering()
1487 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
1488 Subtarget.getCPUDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
1495 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { in PPCTargetLowering()
1513 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive(); in PPCTargetLowering()
1629 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
1630 if (Subtarget.hasAltivec()) in getByValTypeAlignment()
1636 return Subtarget.useSoftFloat(); in useSoftFloat()
1640 return Subtarget.hasSPE(); in hasSPE()
1649 if (!Subtarget.isPPC64() || !Subtarget.hasVSX()) in shallExtractConstSplatVectorElementToStore()
1656 Index = Subtarget.isLittleEndian() ? 2 : 1; in shallExtractConstSplatVectorElementToStore()
1660 Index = Subtarget.isLittleEndian() ? 1 : 0; in shallExtractConstSplatVectorElementToStore()
1842 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1951 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in isVPKUDUMShuffleMask() local
1952 if (!Subtarget.hasP8Vector()) in isVPKUDUMShuffleMask()
2862 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2969 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3068 if (isLoad && usePartialVectorLoads(N, Subtarget)) { in getPreIndexedAddressParts()
3130 static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, in getLabelAccessInfo() argument
3173 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3176 : Subtarget.isAIXABI() in getTOCEntry()
3194 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerConstantPool()
3195 if (Subtarget.isUsingPCRelativeCalls()) { in LowerConstantPool()
3209 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerConstantPool()
3211 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerConstantPool()
3237 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3244 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3261 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3278 if (Subtarget.isUsingPCRelativeCalls()) { in LowerJumpTable()
3289 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerJumpTable()
3297 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerJumpTable()
3299 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerJumpTable()
3317 if (Subtarget.isUsingPCRelativeCalls()) { in LowerBlockAddress()
3328 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerBlockAddress()
3335 if (Subtarget.is32BitELFABI() && isPositionIndependent()) in LowerBlockAddress()
3342 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); in LowerBlockAddress()
3350 if (Subtarget.isAIXABI()) in LowerGlobalTLSAddress()
3366 bool Is64Bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressAIX()
3367 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS(); in LowerGlobalTLSAddressAIX()
3448 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3456 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3477 bool IsPCRel = Subtarget.isUsingPCRelativeCalls(); in LowerGlobalTLSAddressLinux()
3508 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3532 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalTLSAddressLinux()
3572 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { in LowerGlobalAddress()
3573 if (Subtarget.isUsingPCRelativeCalls()) { in LowerGlobalAddress()
3595 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV); in LowerGlobalAddress()
3597 if (IsPIC && Subtarget.isSVR4ABI()) { in LowerGlobalAddress()
3624 assert(!Subtarget.hasP9Vector() && in LowerSETCC()
3697 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3788 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3800 if (Subtarget.isAIXABI()) in LowerADJUST_TRAMPOLINE()
3859 if (Subtarget.isAIXABI()) in LowerINIT_TRAMPOLINE()
3903 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
4103 if (Subtarget.isAIXABI()) in LowerFormalArguments()
4106 if (Subtarget.is64BitELFABI()) in LowerFormalArguments()
4109 assert(Subtarget.is32BitELFABI()); in LowerFormalArguments()
4164 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_32SVR4()
4188 if (Subtarget.hasP8Vector()) in LowerFormalArguments_32SVR4()
4190 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4196 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
4198 else if (Subtarget.hasSPE()) in LowerFormalArguments_32SVR4()
4221 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4227 if (!Subtarget.isLittleEndian()) in LowerFormalArguments_32SVR4()
4281 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_32SVR4()
4385 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerFormalArguments_64SVR4()
4386 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerFormalArguments_64SVR4()
4399 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_64SVR4()
4621 Subtarget.hasP8Vector() in LowerFormalArguments_64SVR4()
4625 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
4717 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_64SVR4()
4852 needStackSlotPassParameters(const PPCSubtarget &Subtarget, in needStackSlotPassParameters() argument
4854 assert(Subtarget.is64BitELFABI()); in needStackSlotPassParameters()
4857 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in needStackSlotPassParameters()
4977 if (CallerCC != CalleeCC && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
4989 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
4994 if (!Subtarget.isUsingPCRelativeCalls() && in IsEligibleForTailCallOptimization_64SVR4()
5011 needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5013 else if (!CB && needStackSlotPassParameters(Subtarget, Outs)) in IsEligibleForTailCallOptimization_64SVR4()
5106 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); in EmitTailCallStoreFPAndRetAddr() local
5107 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in EmitTailCallStoreFPAndRetAddr()
5108 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr()
5147 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5240 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerCallResult()
5251 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5261 if (!Subtarget.isLittleEndian()) in LowerCallResult()
5296 const PPCSubtarget &Subtarget, bool isPatchPoint) { in isIndirectCall() argument
5312 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() && in isIndirectCall()
5320 static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) { in isTOCSaveRestoreRequired() argument
5321 return Subtarget.isAIXABI() || in isTOCSaveRestoreRequired()
5322 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()); in isTOCSaveRestoreRequired()
5327 const PPCSubtarget &Subtarget, in getCallOpcode() argument
5344 RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC in getCallOpcode()
5346 } else if (Subtarget.isUsingPCRelativeCalls()) { in getCallOpcode()
5347 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."); in getCallOpcode()
5349 } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) { in getCallOpcode()
5389 const SDLoc &dl, const PPCSubtarget &Subtarget) { in transformCallee() argument
5390 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI()) in transformCallee()
5409 Subtarget.is32BitELFABI() && !isLocalCallee() && in transformCallee()
5410 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_; in transformCallee()
5413 const TargetMachine &TM = Subtarget.getTargetMachine(); in transformCallee()
5427 if (Subtarget.isAIXABI()) { in transformCallee()
5437 if (Subtarget.isAIXABI()) { in transformCallee()
5500 const PPCSubtarget &Subtarget) { in prepareDescriptorIndirectCall() argument
5529 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors() in prepareDescriptorIndirectCall()
5537 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister(); in prepareDescriptorIndirectCall()
5538 const MCRegister TOCReg = Subtarget.getTOCPointerRegister(); in prepareDescriptorIndirectCall()
5541 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset(); in prepareDescriptorIndirectCall()
5542 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset(); in prepareDescriptorIndirectCall()
5544 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5545 const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in prepareDescriptorIndirectCall()
5574 assert((!hasNest || !Subtarget.isAIXABI()) && in prepareDescriptorIndirectCall()
5593 const PPCSubtarget &Subtarget) { in buildCallOperands() argument
5594 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5616 if (isTOCSaveRestoreRequired(Subtarget)) { in buildCallOperands()
5617 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in buildCallOperands()
5620 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in buildCallOperands()
5627 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest) in buildCallOperands()
5628 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), in buildCallOperands()
5650 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && in buildCallOperands()
5651 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) in buildCallOperands()
5652 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
5655 if (CFlags.IsVarArg && Subtarget.is32BitELFABI()) in buildCallOperands()
5659 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in buildCallOperands()
5677 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) || in FinishCall()
5678 Subtarget.isAIXABI()) in FinishCall()
5683 Subtarget, DAG.getTarget(), CB ? CB->isStrictFP() : false); in FinishCall()
5686 Callee = transformCallee(Callee, DAG, dl, Subtarget); in FinishCall()
5687 else if (Subtarget.usesFunctionDescriptors()) in FinishCall()
5689 dl, CFlags.HasNest, Subtarget); in FinishCall()
5696 SPDiff, Subtarget); in FinishCall()
5707 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && in FinishCall()
5767 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) in isEligibleForTCO()
5770 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in isEligibleForTCO()
5816 assert((Subtarget.isUsingPCRelativeCalls() || in LowerCall()
5833 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) && in LowerCall()
5839 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint), in LowerCall()
5841 Subtarget.is64BitELFABI() && in LowerCall()
5845 if (Subtarget.isAIXABI()) in LowerCall()
5849 assert(Subtarget.isSVR4ABI()); in LowerCall()
5850 if (Subtarget.isPPC64()) in LowerCall()
5897 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(), in LowerCall_32SVR4()
6031 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
6032 bool IsLE = Subtarget.isLittleEndian(); in LowerCall_32SVR4()
6118 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerCall_64SVR4()
6119 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerCall_64SVR4()
6147 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_64SVR4()
6266 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_64SVR4()
6659 if (isTOCSaveRestoreRequired(Subtarget)) { in LowerCall_64SVR4()
6665 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_64SVR4()
6733 const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>( in CC_AIX() local
6735 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
7074 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerFormalArguments_AIX() local
7076 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
7088 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_AIX()
7149 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7150 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7226 const PPCFrameLowering *FL = Subtarget.getFrameLowering(); in LowerFormalArguments_AIX()
7291 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7292 Subtarget.hasVSX())); in LowerFormalArguments_AIX()
7319 EnsureStackAlignment(Subtarget.getFrameLowering(), CallerReservedArea); in LowerFormalArguments_AIX()
7379 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>(); in LowerCall_AIX() local
7390 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_AIX()
7391 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7653 const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister(); in LowerCall_AIX()
7654 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in LowerCall_AIX()
7655 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7657 Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_AIX()
7690 Outs, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in CanLowerReturn()
7705 (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold) in LowerReturn()
7732 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7733 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerReturn()
7786 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE()
7807 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex()
7818 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); in getReturnAddrFrameIndex()
7830 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex()
7841 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); in getFramePointerFrameIndex()
7876 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA()
8018 if (Subtarget.isLittleEndian()) in LowerTRUNCATEVector()
8048 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
8058 Subtarget.hasSPE()) in LowerSELECT_CC()
8065 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
8192 const PPCSubtarget &Subtarget) { in convertFPToInt() argument
8219 if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector()) in convertFPToInt()
8220 DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in convertFPToInt()
8226 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ); in convertFPToInt()
8229 assert((IsSigned || Subtarget.hasFPCVT()) && in convertFPToInt()
8248 SDValue Tmp = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTForReuse()
8254 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8255 (IsSigned || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
8280 MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4); in LowerFP_TO_INTForReuse()
8295 SDValue Conv = convertFPToInt(Op, DAG, Subtarget); in LowerFP_TO_INTDirectMove()
8314 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerFP_TO_INT()
8393 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8421 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8497 if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2) in directMoveIsProfitable()
8519 const PPCSubtarget &Subtarget, in convertIntToFP() argument
8531 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8553 assert(Subtarget.hasFPCVT() && in LowerINT_TO_FPDirectMove()
8561 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
8613 if (Subtarget.isLittleEndian()) in LowerINT_TO_FPVector()
8628 if (Subtarget.hasP9Altivec()) in LowerINT_TO_FPVector()
8665 return Subtarget.hasP9Vector() ? Op : SDValue(); in LowerINT_TO_FP()
8683 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) && in LowerINT_TO_FP()
8684 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8687 assert((IsSigned || Subtarget.hasFPCVT()) && in LowerINT_TO_FP()
8703 !Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8748 } else if (Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8758 } else if (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8768 } else if (((Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
8770 (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
8805 SDValue FP = convertIntToFP(Op, Bits, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8809 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8832 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8865 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
8887 SDValue FP = convertIntToFP(Op, Ld, DAG, Subtarget, Chain); in LowerINT_TO_FP()
8890 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
9280 static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op, in isValidSplatLoad() argument
9283 if (!InputNode || !Subtarget.hasVSX() || !ISD::isUNINDEXEDLoad(InputNode)) in isValidSplatLoad()
9333 HasAnyUndefs, 0, !Subtarget.isLittleEndian()); in LowerBUILD_VECTOR()
9340 Subtarget.hasPrefixInstrs()) { in LowerBUILD_VECTOR()
9384 isValidSplatLoad(Subtarget, Op, NewOpcode)) { in LowerBUILD_VECTOR()
9422 !Subtarget.isLittleEndian() && Subtarget.hasVSX() && in LowerBUILD_VECTOR()
9423 Subtarget.hasLFIWAX())) in LowerBUILD_VECTOR()
9431 if (NumUsesOfInputLD == 1 && Subtarget.isLittleEndian() && in LowerBUILD_VECTOR()
9432 Subtarget.isISA3_1() && ElementSize <= 16) in LowerBUILD_VECTOR()
9437 Subtarget.hasVSX()) { in LowerBUILD_VECTOR()
9457 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
9458 haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove(), in LowerBUILD_VECTOR()
9459 Subtarget.hasP8Vector())) in LowerBUILD_VECTOR()
9485 if (Subtarget.hasPrefixInstrs() && SplatSize == 2) in LowerBUILD_VECTOR()
9489 if (Subtarget.hasPrefixInstrs() && SplatSize == 4) in LowerBUILD_VECTOR()
9494 if (Subtarget.hasP9Vector() && SplatSize == 1) in LowerBUILD_VECTOR()
9597 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR()
9603 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR()
9609 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR()
9700 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTB()
9806 bool IsLE = Subtarget.isLittleEndian(); in lowerToVINSERTH()
9945 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) || in lowerToXXSPLTI32DX()
9957 bool IsLE = Subtarget.isLittleEndian(); in lowerToXXSPLTI32DX()
10034 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVECTOR_SHUFFLE()
10044 if (InputLoad && Subtarget.hasVSX() && V2.isUndef() && in LowerVECTOR_SHUFFLE()
10064 if ((IsFourByte && Subtarget.hasP9Vector()) || !IsFourByte) { in LowerVECTOR_SHUFFLE()
10101 if (Subtarget.hasP9Vector() && in LowerVECTOR_SHUFFLE()
10120 if (Subtarget.hasPrefixInstrs()) { in LowerVECTOR_SHUFFLE()
10126 if (Subtarget.hasP9Altivec()) { in LowerVECTOR_SHUFFLE()
10135 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
10148 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
10161 if (Subtarget.hasP9Vector()) { in LowerVECTOR_SHUFFLE()
10181 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
10215 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10236 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
10315 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVPERM()
10316 bool isPPC64 = Subtarget.isPPC64(); in LowerVPERM()
10318 if (Subtarget.hasVSX() && Subtarget.hasP9Vector() && in LowerVPERM()
10443 bool &isDot, const PPCSubtarget &Subtarget) { in getVectorCompareInfo() argument
10472 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10484 if (Subtarget.hasP9Altivec()) { in getVectorCompareInfo()
10532 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10551 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
10561 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10585 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
10628 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10639 if (Subtarget.hasP9Altivec()) in getVectorCompareInfo()
10681 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10696 if (Subtarget.hasP8Altivec()) in getVectorCompareInfo()
10704 if (!Subtarget.isISA3_1()) in getVectorCompareInfo()
10736 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10741 if (Subtarget.isISAFuture()) { in LowerINTRINSIC_WO_CHAIN()
10754 Subtarget.isLittleEndian() ? Value2 : Value, in LowerINTRINSIC_WO_CHAIN()
10755 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0, in LowerINTRINSIC_WO_CHAIN()
10760 Subtarget.isLittleEndian() ? Value2 : Value, in LowerINTRINSIC_WO_CHAIN()
10761 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1, in LowerINTRINSIC_WO_CHAIN()
10766 Subtarget.isLittleEndian() ? Value : Value2, in LowerINTRINSIC_WO_CHAIN()
10767 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0, in LowerINTRINSIC_WO_CHAIN()
10772 Subtarget.isLittleEndian() ? Value : Value2, in LowerINTRINSIC_WO_CHAIN()
10773 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1, in LowerINTRINSIC_WO_CHAIN()
10791 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10802 if (!Subtarget.isISAFuture()) in LowerINTRINSIC_WO_CHAIN()
10868 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128)) in LowerINTRINSIC_WO_CHAIN()
10918 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) in LowerINTRINSIC_WO_CHAIN()
10993 unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE; in LowerINTRINSIC_VOID()
10994 EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerINTRINSIC_VOID()
11010 if (!Subtarget.isPPC64()) in LowerBSWAP()
11019 if (Subtarget.isLittleEndian()) in LowerBSWAP()
11117 const PPCSubtarget &Subtarget) { in getDataClassTest() argument
11143 SDValue Rev = getDataClassTest(Op, ~Mask, Dl, DAG, Subtarget); in getDataClassTest()
11178 getDataClassTest(Op, Mask & ~fcNormal, Dl, DAG, Subtarget), Result); in getDataClassTest()
11185 SDValue NanCheck = getDataClassTest(Op, fcNan, Dl, DAG, Subtarget); in getDataClassTest()
11193 DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 3 : 0, Dl)); in getDataClassTest()
11196 if (Subtarget.isPPC64()) { in getDataClassTest()
11205 DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 1 : 0, Dl)); in getDataClassTest()
11222 getDataClassTest(Op, Mask & ~fcNan, Dl, DAG, Subtarget), in getDataClassTest()
11254 assert(Subtarget.hasP9Vector() && "Test data class requires Power9"); in LowerIS_FPCLASS()
11259 return getDataClassTest(LHS, Category, Dl, DAG, Subtarget); in LowerIS_FPCLASS()
11293 if (Subtarget.hasP9Vector()) { in LowerINSERT_VECTOR_ELT()
11313 if (Subtarget.isISA3_1()) { in LowerINSERT_VECTOR_ELT()
11314 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
11334 if (Subtarget.isLittleEndian()) { in LowerINSERT_VECTOR_ELT()
11357 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
11359 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
11376 if (Subtarget.isLittleEndian()) { in LowerVectorLoad()
11404 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
11406 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
11412 if (Subtarget.isISAFuture()) { in LowerVectorStore()
11424 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
11426 if (Subtarget.isISAFuture()) { in LowerVectorStore()
11427 VecNum = Subtarget.isLittleEndian() ? 1 - (Idx % 2) : (Idx % 2); in LowerVectorStore()
11477 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerMUL()
11515 !Subtarget.hasP9Vector()) in LowerFP_ROUND()
11557 if (Subtarget.isLittleEndian()) in LowerFP_EXTEND()
11748 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
11846 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitAtomicBinary()
11856 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
11861 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
12020 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in EmitPartwordAtomicBinary()
12039 if (Subtarget.hasPartwordAtomics()) in EmitPartwordAtomicBinary()
12047 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
12048 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitPartwordAtomicBinary()
12233 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjSetJmp()
12234 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo(); in emitEHSjLjSetJmp()
12301 if (Subtarget.is64BitELFABI()) { in emitEHSjLjSetJmp()
12314 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
12316 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
12319 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
12342 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
12345 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
12375 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjLongJmp()
12393 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29 in emitEHSjLjLongJmp()
12456 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
12482 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); in getStackProbeSize()
12505 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca()
12507 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitProbedAlloca()
12669 if (Subtarget.is64BitELFABI() && in EmitInstrWithCustomInserter()
12671 !Subtarget.isUsingPCRelativeCalls()) { in EmitInstrWithCustomInserter()
12691 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitInstrWithCustomInserter()
12944 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12946 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
12958 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
12963 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
13040 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
13041 bool isLittleEndian = Subtarget.isLittleEndian(); in EmitInstrWithCustomInserter()
13317 if (Subtarget.hasDirectMove()) { in EmitInstrWithCustomInserter()
13478 static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { in getEstimateRefinementSteps() argument
13483 int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3; in getEstimateRefinementSteps()
13495 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
13524 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
13535 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
13536 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
13537 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
13538 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
13540 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getSqrtEstimate()
13544 UseOneConstNR = !Subtarget.needsTwoConstNR(); in getSqrtEstimate()
13554 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
13555 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
13556 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
13557 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
13559 RefinementSteps = getEstimateRefinementSteps(VT, Subtarget); in getRecipEstimate()
13576 switch (Subtarget.getCPUDirective()) { in combineRepeatedFPDivisors()
13862 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits"); in DAGCombineTruncBoolExt()
14156 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
14157 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
14821 if (!Subtarget.hasVSX()) in DAGCombineBuildVector()
14844 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
14853 if (Subtarget.isISA3_1()) { in DAGCombineBuildVector()
14891 SubvecIdx = Subtarget.isLittleEndian() ? 1 : 0; in DAGCombineBuildVector()
14893 SubvecIdx = Subtarget.isLittleEndian() ? 0 : 1; in DAGCombineBuildVector()
14910 if (useSoftFloat() || !Subtarget.has64BitSupport()) in combineFPToIntToFP()
14931 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) { in combineFPToIntToFP()
14964 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in combineFPToIntToFP()
14969 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14974 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14981 Subtarget.hasFPCVT()) || in combineFPToIntToFP()
14999 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
15158 if (!Subtarget.hasVSX() || !Subtarget.hasFPCVT() || !isTypeLegal(ResVT)) in combineStoreFPToInt()
15163 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) || in combineStoreFPToInt()
15164 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
15167 if (ResVT == MVT::ppcf128 || (ResVT == MVT::f128 && !Subtarget.hasP9Vector())) in combineStoreFPToInt()
15170 if ((Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) || in combineStoreFPToInt()
15174 Val = convertFPToInt(N->getOperand(1), DAG, Subtarget); in combineStoreFPToInt()
15246 const PPCSubtarget &Subtarget) { in fixupShuffleMaskForPermutedSToV() argument
15251 Subtarget.isLittleEndian() ? HalfVec : HalfVec - ValidLaneWidth; in fixupShuffleMaskForPermutedSToV()
15261 const PPCSubtarget &Subtarget) { in getSToVPermuted() argument
15281 ResultInElt -= Subtarget.isLittleEndian() ? 0 : 1; in getSToVPermuted()
15310 bool IsLittleEndian = Subtarget.isLittleEndian(); in combineVectorShuffle()
15317 if (!Subtarget.hasDirectMove()) in combineVectorShuffle()
15379 SToVLHS = getSToVPermuted(SToVLHS, DAG, Subtarget); in combineVectorShuffle()
15389 SToVRHS = getSToVPermuted(SToVRHS, DAG, Subtarget); in combineVectorShuffle()
15401 HalfVec, ValidLaneWidth, Subtarget); in combineVectorShuffle()
15503 if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX()) in combineVReverseMemOP()
15509 if (!Subtarget.hasP9Vector()) in combineVReverseMemOP()
15666 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15701 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15722 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
15737 if (Subtarget.needsSwapsForVSXMemOps() && in PerformDAGCombine()
15803 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
15852 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && in PerformDAGCombine()
15854 !Subtarget.hasP8Vector() && in PerformDAGCombine()
15861 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
15966 Perm = Subtarget.hasAltivec() in PerformDAGCombine()
15981 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
16028 if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && in PerformDAGCombine()
16079 !Subtarget.isLittleEndian()); in PerformDAGCombine()
16090 if (Subtarget.needsSwapsForVSXMemOps()) in PerformDAGCombine()
16098 if (Subtarget.needsSwapsForVSXMemOps()) { in PerformDAGCombine()
16113 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
16118 (Subtarget.hasLDBRX() && Is64BitBswapOn64BitTgt))) { in PerformDAGCombine()
16170 if (Subtarget.isLittleEndian()) in PerformDAGCombine()
16310 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) { in PerformDAGCombine()
16364 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
16448 switch (Subtarget.getCPUDirective()) { in getPrefLoopAlignment()
16473 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in getPrefLoopAlignment()
16595 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16599 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16607 if (Subtarget.hasSPE()) { in getRegForInlineAsmConstraint()
16620 if (Subtarget.hasAltivec() && VT.isVector()) in getRegForInlineAsmConstraint()
16622 else if (Subtarget.hasVSX()) in getRegForInlineAsmConstraint()
16629 } else if (Constraint == "wc" && Subtarget.useCRBits()) { in getRegForInlineAsmConstraint()
16634 Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16639 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16642 } else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
16643 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16676 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16680 return Subtarget.hasSPE() in getRegForInlineAsmConstraint()
16695 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16708 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) { in getRegForInlineAsmConstraint()
16826 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
16875 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR()
16886 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl, in LowerRETURNADDR()
16931 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName()
16950 if (Subtarget.is32BitELFABI()) in isAccessedAsGotIndirect()
16955 if (Subtarget.isAIXABI()) in isAccessedAsGotIndirect()
16969 return Subtarget.isGVIndirectSymbol(G->getGlobal()); in isAccessedAsGotIndirect()
17142 if (Subtarget.hasAltivec() && Op.size() >= 16) { in getOptimalMemOpType()
17143 if (Op.isMemset() && Subtarget.hasVSX()) { in getOptimalMemOpType()
17153 if (Op.isAligned(Align(16)) || Subtarget.hasP8Vector()) in getOptimalMemOpType()
17158 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
17197 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
17244 !Subtarget.allowsUnalignedFPAccess()) in allowsMisalignedMemoryAccesses()
17248 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
17301 if (Subtarget.hasSPE() || Subtarget.useSoftFloat()) in isFMAFasterThanFMulAndFAdd()
17308 return Subtarget.hasP9Vector(); in isFMAFasterThanFMulAndFAdd()
17381 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
17386 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
17393 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves in shouldExpandBuildVectorWithShuffles()
17395 if (Subtarget.hasVSX()) in shouldExpandBuildVectorWithShuffles()
17402 if (DisableILPPref || Subtarget.enableMachineScheduler()) in getSchedulingPreference()
17495 if (!Subtarget.isTargetLinux()) in useLoadStackGuardNode()
17503 if (Subtarget.isAIXABI()) { in insertSSPDeclarations()
17508 if (!Subtarget.isTargetLinux()) in insertSSPDeclarations()
17513 if (Subtarget.isAIXABI()) in getSDagStackGuard()
17520 if (!VT.isSimple() || !Subtarget.hasVSX()) in isFPImmLegal()
17530 if (Subtarget.hasPrefixInstrs()) { in isFPImmLegal()
17589 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
17632 const PPCSubtarget &Subtarget) { in combineADDToADDZE() argument
17633 if (!Subtarget.isPPC64()) in combineADDToADDZE()
17718 const PPCSubtarget &Subtarget) { in combineADDToMAT_PCREL_ADDR() argument
17719 if (!Subtarget.isUsingPCRelativeCalls()) in combineADDToMAT_PCREL_ADDR()
17759 if (auto Value = combineADDToADDZE(N, DCI.DAG, Subtarget)) in combineADD()
17762 if (auto Value = combineADDToMAT_PCREL_ADDR(N, DCI.DAG, Subtarget)) in combineADD()
17780 if (Subtarget.useCRBits()) { in combineTRUNCATE()
17833 switch (this->Subtarget.getCPUDirective()) { in combineMUL()
17944 if (!Subtarget.is64BitELFABI()) in mayBeEmittedAsTailCall()
18112 if (!Subtarget.hasP9Vector()) in computeMOFlags()
18116 if (Subtarget.hasPrefixInstrs()) in computeMOFlags()
18119 if (Subtarget.hasSPE()) in computeMOFlags()
18129 if (Subtarget.isISA3_1() && ((ParentOp == ISD::INTRINSIC_W_CHAIN) || in computeMOFlags()
18167 assert(Subtarget.pairedVectorMemops() && in computeMOFlags()
18251 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
18421 assert(Subtarget.isUsingPCRelativeCalls() && in SelectOptimalAddrMode()
18472 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18528 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18549 return Subtarget.isPPC64() && Subtarget.hasQuadwordAtomics(); in shouldInlineQuadwordAtomics()