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Searched refs:SubIdx (Results 1 – 25 of 63) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp158 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
162 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
164 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
182 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
183 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
232 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
234 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
238 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
241 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
245 DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
[all …]
H A DExpandPostRAPseudos.cpp69 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
71 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
H A DTargetRegisterInfo.cpp113 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
114 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
134 if (SubIdx) { in printReg()
136 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
138 OS << ":sub(" << SubIdx << ')'; in printReg()
H A DPeepholeOptimizer.cpp507 unsigned SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
508 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
531 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
557 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
651 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1987 if (RegSeqInput.SubIdx == DefSubReg) in getNextSourceFromRegSequence()
2024 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
2043 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none()) in getNextSourceFromInsertSubreg()
2076 ExtractSubregInputReg.SubIdx); in getNextSourceFromExtractSubreg()
H A DRegisterCoalescer.cpp1817 unsigned SubIdx) { in updateRegDefsUses() argument
1854 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr()) in updateRegDefsUses()
1864 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1875 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1895 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
2415 const unsigned SubIdx; member in __anon958e62000311::JoinVals
2593 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2656 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
2980 LaneBitmask OtherMask = TRI->getSubRegIndexLaneMask(Other.SubIdx); in analyzeValue()
3119 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
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H A DMachineOperand.cpp83 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
86 if (SubIdx && getSubReg()) in substVirtReg()
87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
89 if (SubIdx) in substVirtReg()
90 setSubReg(SubIdx); in substVirtReg()
H A DTargetInstrInfo.cpp389 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
393 if (!SubIdx) { in getStackSlotRange()
398 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
403 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
420 Register DestReg, unsigned SubIdx, in reMaterialize() argument
424 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1639 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1667 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
H A DLiveRangeEdit.cpp186 bool Late, unsigned SubIdx, in rematerializeAt() argument
189 TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri); in rematerializeAt()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp131 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
132 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
138 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
144 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
535 if (!SubIdx) in computeSecondarySubRegs()
1124 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1929 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1933 if (SuperIdx == SubIdx) in pruneUnitSets()
1954 SuperSetIDs.push_back(SubIdx); in pruneUnitSets()
2292 if (SubIdx.Artificial) in inferSubClassWithSubReg()
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H A DCodeGenRegisters.h390 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
391 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
404 const CodeGenSubRegIndex *SubIdx) const;
406 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
408 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
413 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
417 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
419 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
H A DGlobalISelEmitter.cpp1412 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in createAndImportSubInstructionRenderer() local
1413 if (!SubIdx) in createAndImportSubInstructionRenderer()
1457 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in createAndImportSubInstructionRenderer() local
1458 if (!SubIdx) in createAndImportSubInstructionRenderer()
1585 RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx); in importExplicitUseRenderers()
1596 std::get<2>(*SubOperand), SubIdx); in importExplicitUseRenderers()
1629 DstMIBuilder.addRenderer<SubRegIndexRenderer>(SubIdx); in importExplicitUseRenderers()
2112 auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1)); in runOnPattern() local
2113 if (!SubIdx) in runOnPattern()
2182 auto SubIdx = inferSubRegIndexForNode(SubRegChild); in runOnPattern() local
[all …]
H A DRegisterBankEmitter.cpp201 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses() local
203 PossibleSubclass.getSuperRegClasses(&SubIdx, BV); in visitRegisterBankClasses()
H A DCodeGenTarget.h126 const CodeGenSubRegIndex *SubIdx,
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h377 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
378 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
380 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
387 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
388 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
389 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
613 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
615 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1339 unsigned SubIdx = 0,
H A DTargetInstrInfo.h263 Register &DstReg, unsigned &SubIdx) const { in isCoalescableExtInstr() argument
364 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
413 unsigned SubIdx, const MachineInstr &Orig,
520 unsigned SubIdx; member
523 unsigned SubIdx = 0)
524 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
H A DLiveRangeEdit.h215 bool Late = false, unsigned SubIdx = 0,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp178 unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit; in INITIALIZE_PASS_DEPENDENCY() local
181 SubIdx = 0; in INITIALIZE_PASS_DEPENDENCY()
190 .addReg(R, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp213 SubIdx = X86::sub_32bit; in getSubRegIndex()
215 SubIdx = X86::sub_16bit; in getSubRegIndex()
217 SubIdx = X86::sub_8bit; in getSubRegIndex()
220 return SubIdx; in getSubRegIndex()
792 unsigned SubIdx; in selectTruncOrPtrToInt() local
797 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
801 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
1261 SubIdx = X86::sub_xmm; in emitExtractSubreg()
1263 SubIdx = X86::sub_ymm; in emitExtractSubreg()
1300 SubIdx = X86::sub_xmm; in emitInsertSubreg()
[all …]
H A DX86LegalizerInfo.cpp486 unsigned SubIdx = Query.Opcode == G_EXTRACT ? 0 : 1; in X86LegalizerInfo() local
488 return (HasAVX && typePairInSet(SubIdx, FullIdx, in X86LegalizerInfo()
493 (HasAVX512 && typePairInSet(SubIdx, FullIdx, in X86LegalizerInfo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
H A DThumbRegisterInfo.h41 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
H A DARMBaseRegisterInfo.h212 const DebugLoc &dl, Register DestReg, unsigned SubIdx,
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp449 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg() argument
498 unsigned SubIdx = Node->getConstantOperandVal(1); in EmitSubregNode() local
517 SubIdx == DefSubIdx && in EmitSubregNode()
533 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
545 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
547 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
554 unsigned SubIdx = N2->getAsZExtVal(); in EmitSubregNode() local
572 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
593 MIB.addImm(SubIdx); in EmitSubregNode()
653 unsigned SubIdx = Op->getAsZExtVal(); in EmitRegSequence() local
[all …]
H A DInstrEmitter.h85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
27 if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx)) in getMatchingSuperReg()

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