449 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,  in ConstrainForSubReg()  argument
452   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);  in ConstrainForSubReg()
465   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);  in ConstrainForSubReg()
498     unsigned SubIdx = Node->getConstantOperandVal(1);  in EmitSubregNode()  local
517         SubIdx == DefSubIdx &&  in EmitSubregNode()
533         Reg = ConstrainForSubReg(Reg, SubIdx,  in EmitSubregNode()
545         CopyMI.addReg(Reg, 0, SubIdx);  in EmitSubregNode()
547         CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));  in EmitSubregNode()
554     unsigned SubIdx = N2->getAsZExtVal();  in EmitSubregNode()  local
572     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);  in EmitSubregNode()
593     MIB.addImm(SubIdx);  in EmitSubregNode()
653         unsigned SubIdx = Op->getAsZExtVal();  in EmitRegSequence()  local
657         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);  in EmitRegSequence()