Searched refs:SrcReg0 (Results 1 – 4 of 4) sorted by relevance
434 Register SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement() local455 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()467 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
4749 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local4752 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()6617 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local6635 if (SrcReg0.isVirtual()) in genFusedMultiply()6636 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()6682 Register SrcReg0 = MAD->getOperand(1).getReg(); in genFNegatedMAD() local6690 if (SrcReg0.isVirtual()) in genFNegatedMAD()6691 MRI.constrainRegClass(SrcReg0, RC); in genFNegatedMAD()6848 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local6855 if (SrcReg0.isVirtual()) in genMaddR()[all …]
1413 Register SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local1416 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()
2557 Register SrcReg0 = MI.getOperand(1).getReg(); in applyMappingImpl() local2571 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()2587 B.buildTrunc(Op0L, SrcReg0); in applyMappingImpl()