Lines Matching refs:SrcReg0
4749 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
4752 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
4758 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
6617 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
6635 if (SrcReg0.isVirtual()) in genFusedMultiply()
6636 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
6645 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6651 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6657 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6682 Register SrcReg0 = MAD->getOperand(1).getReg(); in genFNegatedMAD() local
6690 if (SrcReg0.isVirtual()) in genFNegatedMAD()
6691 MRI.constrainRegClass(SrcReg0, RC); in genFNegatedMAD()
6699 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFNegatedMAD()
6848 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
6855 if (SrcReg0.isVirtual()) in genMaddR()
6856 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
6864 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()