Searched refs:Src0SubRC (Results 1 – 2 of 2) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 7669 const TargetRegisterClass *Src0SubRC = in splitScalar64BitUnaryOp() local
7731 const TargetRegisterClass *Src0SubRC = in splitScalarSMulU64() local
7733 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulU64()
7734 Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); in splitScalarSMulU64()
7743 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in splitScalarSMulU64()
7747 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in splitScalarSMulU64()
7840 const TargetRegisterClass *Src0SubRC = in splitScalarSMulPseudo() local
7842 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulPseudo()
7843 Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); in splitScalarSMulPseudo()
7852 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in splitScalarSMulPseudo()
[all …]
|
| H A D | SIISelLowering.cpp | 4835 const TargetRegisterClass *Src0SubRC = in EmitInstrWithCustomInserter() local
4841 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
4846 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
5064 const TargetRegisterClass *Src0SubRC = in EmitInstrWithCustomInserter() local
5070 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5075 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
|