7669   const TargetRegisterClass *Src0SubRC =  in splitScalar64BitUnaryOp()  local
7673                                                        AMDGPU::sub0, Src0SubRC);  in splitScalar64BitUnaryOp()
7684                                                        AMDGPU::sub1, Src0SubRC);  in splitScalar64BitUnaryOp()
7731   const TargetRegisterClass *Src0SubRC =  in splitScalarSMulU64()  local
7733   if (RI.isSGPRClass(Src0SubRC))  in splitScalarSMulU64()
7734     Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC);  in splitScalarSMulU64()
7743       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulU64()
7747       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);  in splitScalarSMulU64()
7840   const TargetRegisterClass *Src0SubRC =  in splitScalarSMulPseudo()  local
7842   if (RI.isSGPRClass(Src0SubRC))  in splitScalarSMulPseudo()
7843     Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC);  in splitScalarSMulPseudo()
7852       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulPseudo()
7903   const TargetRegisterClass *Src0SubRC =  in splitScalar64BitBinaryOp()  local
7913                                                        AMDGPU::sub0, Src0SubRC);  in splitScalar64BitBinaryOp()
7917                                                        AMDGPU::sub1, Src0SubRC);  in splitScalar64BitBinaryOp()