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Searched refs:SimpleTy (Results 1 – 25 of 68) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineValueType.h63 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
64 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
65 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
66 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
67 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
68 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
123 return SimpleTy == MVT::aarch64svcount; in isScalableTargetExtVT()
178 switch (SimpleTy) { in isOverloaded()
260 switch (SimpleTy) { in getVectorElementType()
274 switch (SimpleTy) { in getVectorMinNumElements()
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H A DValueTypes.h48 if (V.SimpleTy != VT.V.SimpleTy)
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
85 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
130 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
490 return V.SimpleTy; in getRawBits()
499 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
502 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h1010 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
1049 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
1053 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1643 return RegisterTypeForVT[VT.SimpleTy]; in getRegisterType()
2444 RegClassForVT[VT.SimpleTy] = RC; in addRegisterClass()
2482 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift); in setLoadExtAction()
2483 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift; in setLoadExtAction()
2500 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action; in setTruncStoreAction()
2584 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
3537 unsigned Ty = (unsigned)VT.SimpleTy; in setIndexedModeAction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp133 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32)) in CC_AArch64_Custom_Block()
135 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
137 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
141 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
162 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1; in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp320 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1169 switch (RetVT.SimpleTy) { in emitAddSub()
1188 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1473 switch (VT.SimpleTy) { in emitCmp()
1828 switch (VT.SimpleTy) { in emitLoad()
2058 switch (VT.SimpleTy) { in emitStoreRelease()
2117 switch (VT.SimpleTy) { in emitStore()
2676 switch (VT.SimpleTy) { in selectSelect()
4093 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4196 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp865 switch (VT.getSimpleVT().SimpleTy) { in getLdStRegType()
1153 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1723 Value.getNode()->getSimpleValueType(0).SimpleTy; in tryStore()
1935 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryStoreVector()
2053 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
3655 switch (SrcTy.SimpleTy) { in GetConvertOpcode()
3659 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3670 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3681 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3692 switch (DestTy.SimpleTy) { in GetConvertOpcode()
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H A DNVPTXTargetTransformInfo.cpp419 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h91 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
94 bool V = count(T.SimpleTy); in insert()
95 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
105 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
705 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp78 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
H A DDAGISelMatcherGen.cpp41 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
48 assert(VVT.isSimple() && VVT.getSimple().SimpleTy == VT && in getRegisterValueType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp229 auto isHvxTy = [this, IncludeBool](MVT SimpleTy) { in isTypeForHVX() argument
230 if (isHVXVectorType(SimpleTy, IncludeBool)) in isTypeForHVX()
232 auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy); in isTypeForHVX()
241 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() local
242 if (SimpleTy.isValid() && isHvxTy(SimpleTy)) in isTypeForHVX()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp334 switch (VT.SimpleTy) { in X86FastEmitLoad()
1923 switch (VT.SimpleTy) { in X86SelectDivRem()
2669 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2809 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2998 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3165 switch (VT.SimpleTy) { in fastLowerArguments()
3731 switch (VT.SimpleTy) { in X86MaterializeInt()
3751 switch (VT.SimpleTy) { in X86MaterializeInt()
3788 switch (VT.SimpleTy) { in X86MaterializeFP()
3900 switch (VT.SimpleTy) { in fastMaterializeConstant()
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H A DX86ISelDAGToDAG.cpp4774 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4780 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4785 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
5331 switch (NVT.SimpleTy) { in Select()
5408 switch (NVT.SimpleTy) { in Select()
5490 switch (NVT.SimpleTy) { in Select()
5613 switch (NVT.SimpleTy) { in Select()
5621 switch (NVT.SimpleTy) { in Select()
5632 switch (NVT.SimpleTy) { in Select()
5694 switch (NVT.SimpleTy) { in Select()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp233 MVT MT1 = VT1.getSimpleVT().SimpleTy; in isZExtFree()
234 MVT MT2 = VT2.getSimpleVT().SimpleTy; in isZExtFree()
351 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
352 switch (SimpleTy) { in LowerFormalArguments()
364 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp40 switch (Type.SimpleTy) { in toValType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp87 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
H A DAMDGPUTargetTransformInfo.cpp544 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost()
722 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getIntrinsicInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp148 switch (VT.SimpleTy) { in selectIndexedLoad()
192 if (VT.SimpleTy == MVT::i8 && Offs == 1 && Bank == 0) in selectIndexedProgMemLoad()
401 switch (VT.SimpleTy) { in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
335 switch (VT.SimpleTy) { in tryIndexedLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp162 switch (V.SimpleTy) { in getEVTString()
204 switch (V.SimpleTy) { in getTypeForEVT()
648 if (SimpleTy == INVALID_SIMPLE_VALUE_TYPE) in print()
H A DTargetLoweringBase.cpp613 switch (VT.SimpleTy) { \ in getSYNC()
788 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
1010 assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); in getTypeConversion()
1011 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1308 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1582 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp802 switch (VT.SimpleTy) { in ARMSimplifyAddress()
858 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
905 switch (VT.SimpleTy) { in ARMEmitLoad()
1044 switch (VT.SimpleTy) { in ARMEmitStore()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1815 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1908 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3048 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.cpp198 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp757 switch (VT.SimpleTy) { in emitLoad()
811 switch (VT.SimpleTy) { in emitStore()
1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()

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