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Searched refs:ShiftTy (Results 1 – 13 of 13) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp875 ARM_AM::ShiftOpc ShiftTy; member
885 ARM_AM::ShiftOpc ShiftTy; member
892 ARM_AM::ShiftOpc ShiftTy; member
3823 Op->PostIdxReg.ShiftTy = ShiftTy; in CreatePostIdxReg()
4163 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
4190 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
4191 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
4198 ShiftTy = ARM_AM::lsl; in tryParseShiftRegister()
10302 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
10327 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1251 LLT ShiftTy = MRI.getType(ShiftNo); in legalizeFunnelShift() local
1257 APInt BitWidth(ShiftTy.getSizeInBits(), OperationTy.getSizeInBits(), false); in legalizeFunnelShift()
1270 if (ShiftTy.getSizeInBits() == 64 && MI.getOpcode() == TargetOpcode::G_FSHR && in legalizeFunnelShift()
H A DAArch64InstructionSelector.cpp3105 const LLT ShiftTy = MRI.getType(ShiftReg); in select() local
3108 ShiftTy.getSizeInBits() == 64) { in select()
3109 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp786 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
798 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
809 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
810 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
816 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
817 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2771 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2817 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1871 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local
1872 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2489 static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) { in getMidVTForTruncRightShiftCombine() argument
2490 const unsigned ShiftSize = ShiftTy.getScalarSizeInBits(); in getMidVTForTruncRightShiftCombine()
2495 return ShiftTy.changeElementSize(32); in getMidVTForTruncRightShiftCombine()
2503 return ShiftTy; in getMidVTForTruncRightShiftCombine()
6445 LLT ShiftTy = TrueTy.isVector() ? TrueTy.getElementType() : TrueTy; in tryFoldSelectOfConstants() local
6446 auto ShAmtC = B.buildConstant(ShiftTy, TrueValue.exactLogBase2()); in tryFoldSelectOfConstants()
H A DLegalizerHelper.cpp2065 LLT ShiftTy = SrcTy; in widenScalarExtract() local
2068 ShiftTy = WideTy; in widenScalarExtract()
2072 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5041 EVT ShiftTy = in SimplifySetCC() local
5050 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC()
5068 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() local
5079 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
5107 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
10238 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointMul() local
10240 DAG.getConstant(Scale, dl, ShiftTy)); in expandFixedPointMul()
10268 DAG.getConstant(VTSize - 1, dl, ShiftTy)); in expandFixedPointMul()
10335 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointDiv() local
10338 DAG.getConstant(LHSShift, dl, ShiftTy)); in expandFixedPointDiv()
[all …]
H A DSelectionDAGBuilder.cpp3397 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
3402 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
3403 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && in visitShift()
3405 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); in visitShift()
5689 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local
5694 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
5698 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
H A DLegalizeIntegerTypes.cpp4585 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
4586 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4587 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp5276 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local
5279 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost()
5455 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local
5458 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
H A DX86ISelLowering.cpp49534 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
49535 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
49540 Shift.getConstantOperandAPInt(1) != (ShiftTy.getSizeInBits() - 1)) in foldXorTruncShiftIntoCmp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1706 …multiclass adrShiftPat<ValueType Ty, ValueType PredTy, ValueType ShiftTy, Instruction DestAdrIns, …
1710 (Ty (splat_vector (ShiftTy ShiftAmt)))))),