875     ARM_AM::ShiftOpc ShiftTy;  member
885     ARM_AM::ShiftOpc ShiftTy;  member
892     ARM_AM::ShiftOpc ShiftTy;  member
1446     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isPostIdxReg()
2550       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
2561       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
3302                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
3640     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
3653     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
3818   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3823     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
3961     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
3962       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
3984        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "  in print()
3989        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"  in print()
4137   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)  in tryParseShiftRegister()  local
4146   if (ShiftTy == ARM_AM::no_shift)  in tryParseShiftRegister()
4163   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
4190           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
4191           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
4198         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
4214   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
4215     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,  in tryParseShiftRegister()
4219     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
5513   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
5517     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
5524   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,  in parsePostIdxReg()
10302     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10305     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10306     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10307     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10308     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10310     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
10327     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10330     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10331     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10332     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10333     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10339     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
10341     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()