Searched refs:ShiftReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1493 Register ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1513 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1524 .addReg(ShiftReg) in EmitShiftInstr()
1525 .addReg(ShiftReg); in EmitShiftInstr()
1528 .addReg(ShiftReg); in EmitShiftInstr()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1863 Register ShiftReg = RI.createVirtualRegister(RC); in insertShift() local
1875 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); in insertShift()
1877 ShiftMI.addReg(ShiftReg); in insertShift()
1885 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 887 unsigned ShiftReg; member
1386 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2548 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3637 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3642 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3985 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4162 int ShiftReg = 0; in tryParseShiftRegister() local
4167 ShiftReg = SrcReg; in tryParseShiftRegister()
4202 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4203 if (ShiftReg == -1) { in tryParseShiftRegister()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1827 Register ShiftReg = Shl.getReg(2); in matchCommuteShift() local
1840 !mi_match(ShiftReg, MRI, m_ICstOrSplat(C2Val))) in matchCommuteShift()
1848 auto S1 = B.buildShl(SrcTy, X, ShiftReg); in matchCommuteShift()
1849 auto S2 = B.buildShl(SrcTy, C1, ShiftReg); in matchCommuteShift()
6228 Register ShiftReg = MI.getOperand(2).getReg(); in matchShiftsTooBig() local
6234 return matchUnaryPredicate(MRI, ShiftReg, IsShiftTooBig); in matchShiftsTooBig()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3104 Register ShiftReg = I.getOperand(2).getReg(); in select() local
3105 const LLT ShiftTy = MRI.getType(ShiftReg); in select()
3112 .addReg(ShiftReg, 0, AArch64::sub_32); in select()
7445 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister() local
7447 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits(); in selectShiftedRegister()
7451 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12076 Register ShiftReg = in EmitPartwordAtomicBinary() local
12132 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
12157 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12185 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12225 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
13068 Register ShiftReg = in EmitInstrWithCustomInserter() local
13131 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
13147 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
13150 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
13161 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
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