Lines Matching refs:ShiftReg
887 unsigned ShiftReg; member
1386 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2548 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3637 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3642 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3985 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4162 int ShiftReg = 0; in tryParseShiftRegister() local
4167 ShiftReg = SrcReg; in tryParseShiftRegister()
4202 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4203 if (ShiftReg == -1) { in tryParseShiftRegister()
4214 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4216 ShiftReg, Imm, in tryParseShiftRegister()