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Searched refs:SREM (Results 1 – 25 of 44) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1351 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1355 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1359 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1363 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1368 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1372 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1376 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1380 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2092 case ISD::SREM: in maybeLoweredToCall()
H A DARMISelLowering.cpp202 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
286 setOperationAction(ISD::SREM, VT, Expand); in addMVEVectorTypes()
1233 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
1240 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
10588 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
10726 case ISD::SREM: in ReplaceNodeResults()
20657 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
20660 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
20675 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
20678 N->getOpcode() == ISD::SREM; in getDivRemArgList()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h244 SREM, enumerator
H A DBasicTTIImpl.h923 if (ISD == ISD::UREM || ISD == ISD::SREM) {
924 bool IsSigned = ISD == ISD::SREM;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp316 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
326 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
398 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
439 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
511 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
531 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
554 { ISD::SREM, MVT::v16i32, { 17 } }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
572 { ISD::SREM, MVT::v16i16, { 8 } }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
577 { ISD::SREM, MVT::v8i32, { 19 } }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
627 { ISD::SREM, MVT::v8i16, { 8 } }, // pmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1923 case ISD::SREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2045 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2046 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp234 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
281 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
332 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2045 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp104 setOperationAction(ISD::SREM, VT, Custom); in BPFTargetLowering()
314 case ISD::SREM: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp347 case ISD::SREM: in LegalizeOp()
1135 case ISD::SREM: in Expand()
1836 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h546 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
H A DSelectionDAGDumper.cpp249 case ISD::SREM: return "srem"; in getOperationName()
H A DLegalizeDAG.cpp3697 case ISD::SREM: in ExpandNode()
4798 case ISD::SREM: in ConvertNodeToLibcall()
5051 case ISD::SREM: in PromoteNode()
5073 case ISD::SREM: in PromoteNode()
H A DSelectionDAG.cpp3807 case ISD::SREM: { in computeKnownBits()
4627 case ISD::SREM: in ComputeNumSignBits()
5942 case ISD::SREM: in FoldValue()
6030 case ISD::SREM: in isUndef()
6646 case ISD::SREM: in getNode()
6994 case ISD::SREM: in getNode()
7016 case ISD::SREM: in getNode()
H A DFastISel.cpp1782 return selectBinaryOp(I, ISD::SREM); in selectOperator()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp527 ISD::SREM, ISD::SRL, ISD::SSHLSAT, ISD::SSUBO, in NVPTXTargetLowering()
692 setI16x2OperationAction(ISD::SREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
726 ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, in NVPTXTargetLowering()
2730 case ISD::SREM: in LowerOperation()
5322 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
5331 bool IsSigned = N->getOpcode() == ISD::SREM; in PerformREMCombine()
5672 case ISD::SREM: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp137 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
143 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp988 case ISD::SREM: in canOpTrap()
1863 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def195 HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp157 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
158 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4613 case ISD::SREM: in selectRem()
5109 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
5110 return selectRem(I, ISD::SREM); in fastSelectInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp110 setOperationAction(ISD::SREM, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp58 setOperationAction(ISD::SREM, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp258 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
304 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
2775 return DAG.getNode(ISD::SREM, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1676 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1683 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1580 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1627 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()

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