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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
104 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6,
105 SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,
106 SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp64 case SP::JMPLrr: in printSparcAliasInstr()
88 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
89 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
184 case SP::BPFCC: in printCCOperand()
188 case SP::MOVFCCrr: case SP::V9MOVFCCrr: in printCCOperand()
189 case SP::MOVFCCri: case SP::V9MOVFCCri: in printCCOperand()
190 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: in printCCOperand()
191 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: in printCCOperand()
192 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC: in printCCOperand()
201 case SP::BPR: in printCCOperand()
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H A DSparcMCCodeEmitter.cpp104 case SP::TLS_CALL: SymOpNo = 1; break; in encodeInstruction()
105 case SP::GDOP_LDrr: in encodeInstruction()
106 case SP::GDOP_LDXrr: in encodeInstruction()
107 case SP::TLS_ADDrr: in encodeInstruction()
108 case SP::TLS_LDrr: in encodeInstruction()
109 case SP::TLS_LDXrr: SymOpNo = 3; break; in encodeInstruction()
186 if (MI.getOpcode() == SP::TLS_CALL) { in getCallTargetOpValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp53 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
164 return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA || in isI32CondBranchOpcode()
165 Opc == SP::BPICCNT || Opc == SP::BPICCANT; in isI32CondBranchOpcode()
169 return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT || in isI64CondBranchOpcode()
174 return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT || in isRegCondBranchOpcode()
179 return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 || in isFCondBranchOpcode()
189 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
217 case SP::BA: in getBranchDestBlock()
236 case SP::BPR: in getBranchDestBlock()
405 case SP::BA: in isBranchOffsetInRange()
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H A DSparcFrameLowering.cpp64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
82 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
225 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
312 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) in verifyLeafProcRegUse()
343 unsigned mapped_reg = reg - SP::I0 + SP::O0; in remapRegsForLeafProc()
362 MBB.addLiveIn(reg - SP::I0_I1 + SP::O0_O1); in remapRegsForLeafProc()
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H A DSparcRegisterInfo.cpp56 Reserved.set(SP::G1); in getReservedRegs()
68 Reserved.set(SP::O6); in getReservedRegs()
69 Reserved.set(SP::I6); in getReservedRegs()
70 Reserved.set(SP::I7); in getReservedRegs()
71 Reserved.set(SP::G0); in getReservedRegs()
142 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
147 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
160 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
162 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) in replaceFI()
165 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
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H A DDelaySlotFiller.cpp179 if (Opc == SP::RET || Opc == SP::TLS_CALL) in findDelayInstr()
182 if (Opc == SP::RETL || Opc == SP::TAIL_CALL || Opc == SP::TAIL_CALLri) { in findDelayInstr()
276 Opcode >= SP::LDDArr && Opcode <= SP::LDrr) in delayHasHazard()
282 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) in delayHasHazard()
386 if (reg < SP::I0 || reg > SP::I7) in combineRestoreADD()
398 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
414 if (reg < SP::I0 || reg > SP::I7) in combineRestoreOR()
437 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
452 if (reg < SP::I0 || reg > SP::I7) in combineRestoreSETHIi()
471 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
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H A DSparcAsmPrinter.cpp110 CallInst.setOpcode(SP::CALL); in EmitCall()
118 RDPCInst.setOpcode(SP::RDASR); in EmitRDPC()
129 SETHIInst.setOpcode(SP::SETHIi); in EmitSETHI()
186 assert(MO.getReg() != SP::O7 && in LowerGETPCXAndEmitMCInsts()
280 case SP::GETPCX: in emitInstruction()
298 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; in emitFunctionBodyStart()
304 if (reg == SP::G6 || reg == SP::G7) in emitFunctionBodyStart()
320 if (MI->getOpcode() == SP::CALL) in printOperand()
323 else if (MI->getOpcode() == SP::SETHIi) in printOperand()
334 else if (MI->getOpcode() == SP::TLS_CALL) in printOperand()
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H A DLeonPasses.cpp52 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) { in runOnMachineFunction()
54 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
87 if (Opcode == SP::CALL && MI.getNumOperands() > 0) { in runOnMachineFunction()
146 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) { in runOnMachineFunction()
148 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
152 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
H A DSparcISelLowering.cpp62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Split_64()
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_Ret_Split_64()
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7, in toCallerWindow()
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in LowerFormalArguments_32()
1149 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3) in getRegisterByName()
1150 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7) in getRegisterByName()
1151 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3) in getRegisterByName()
1152 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7) in getRegisterByName()
1153 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3) in getRegisterByName()
1154 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7) in getRegisterByName()
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H A DSparcISelDAGToDAG.cpp147 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout())); in SelectADDRrr()
221 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID)) in tryInlineAsm()
237 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass); in tryInlineAsm()
248 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
272 CurDAG->getTargetConstant(SP::IntPairRegClassID, dl, in tryInlineAsm()
275 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32), in tryInlineAsm()
277 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32), in tryInlineAsm()
283 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass); in tryInlineAsm()
299 Flag.setRegClass(SP::IntPairRegClassID); in tryInlineAsm()
359 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); in Select()
[all …]
/freebsd-14.2/usr.bin/procstat/tests/
H A Dprocstat_test.sh30 SP='[[:space:]]'
56 line_format="$SP*%s$SP+%s$SP+%s$SP+%s$SP*"
80 line_format="$SP*%s$SP+%s$SP+%s$SP*"
105 line_format="$SP*%s$SP+%s$SP+%s$SP*"
127 line_format="$SP*%s$SP+%s$SP+%s$SP+%s$SP+%s$SP+%s$SP+%s$SP+%s$SP+%s$SP%s$SP*"
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/orc/tests/unit/
H A Dstring_pool_test.cpp17 StringPool SP; in TEST() local
18 auto P1 = SP.intern("hello"); in TEST()
22 auto P2 = SP.intern(S); in TEST()
24 auto P3 = SP.intern("goodbye"); in TEST()
36 StringPool SP; in TEST() local
37 auto Foo = SP.intern("foo"); in TEST()
42 StringPool SP; in TEST() local
44 auto P1 = SP.intern("s1"); in TEST()
45 SP.clearDeadEntries(); in TEST()
48 SP.clearDeadEntries(); in TEST()
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/freebsd-14.2/crypto/heimdal/appl/ftp/ftpd/
H A Dftpcmd.y95 SP CRLF COMMA
268 | ALLO SP NUMBER SP R SP NUMBER CRLF check_secure
453 | SITE SP HELP SP STRING CRLF check_secure
466 | SITE SP UMASK SP octal_number CRLF check_login_no_guest
479 | SITE SP CHMOD SP octal_number SP pathname CRLF check_login_no_guest
500 | SITE SP IDLE SP NUMBER CRLF check_secure
517 | SITE SP KAUTH SP STRING CRLF check_login
530 | SITE SP KRBTKFILE SP STRING CRLF check_login
545 | SITE SP AFSLOG SP STRING CRLF check_login
558 | SITE SP LOCATE SP STRING CRLF check_login
[all …]
/freebsd-14.2/libexec/ftpd/
H A Dftpcmd.y101 SP CRLF COMMA
419 | ALLO check_login SP NUMBER SP R SP NUMBER CRLF
575 | SITE SP HELP SP STRING CRLF
580 | SITE SP MDFIVE check_login SP pathname CRLF
604 | SITE SP UMASK check_login SP octal_number CRLF
619 | SITE SP CHMOD check_login_ro SP octal_number SP pathname CRLF
639 | SITE SP check_login IDLE SP NUMBER CRLF
1324 return (SP);
1359 return (SP);
1389 return (SP);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DJMCInstrumenter.cpp72 std::string getFlagName(DISubprogram &SP, bool UseX86FastCall) { in getFlagName() argument
80 SP.getDirectory().contains("\\") || in getFlagName()
81 SP.getFilename().contains("\\") in getFlagName()
89 SmallString<256> FilePath(SP.getDirectory()); in getFlagName()
90 sys::path::append(FilePath, PathStyle, SP.getFilename()); in getFlagName()
111 void attachDebugInfo(GlobalVariable &GV, DISubprogram &SP) { in attachDebugInfo() argument
113 DICompileUnit *CU = SP.getUnit(); in attachDebugInfo()
168 auto *SP = F.getSubprogram(); in runImpl() local
169 if (!SP) in runImpl()
172 Constant *&Flag = SavedFlags[SP]; in runImpl()
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/freebsd-14.2/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-c64x.pl106 || STDW B3:B2,*SP[4]
409 STDW B13:B12,*SP[9]
411 STDW B11:B10,*SP[8]
413 STW RA, *SP[15]
523 LDW *SP[15],RA
558 STDW B13:B12,*SP[9]
560 STDW B11:B10,*SP[8]
562 STW RA, *SP[15]
626 STDW RA:BSZ,*SP[4]
721 LDW *SP[15],RA
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp143 .addReg(ARC::SP) in emitPrologue()
149 .addReg(ARC::SP, RegState::Define) in emitPrologue()
151 .addReg(ARC::SP) in emitPrologue()
161 .addReg(ARC::SP) in emitPrologue()
162 .addReg(ARC::SP) in emitPrologue()
190 .addReg(ARC::SP) in emitPrologue()
288 .addReg(ARC::SP) in emitEpilogue()
303 .addReg(ARC::SP) in emitEpilogue()
315 .addReg(ARC::SP) in emitEpilogue()
330 .addReg(ARC::SP) in emitEpilogue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp130 .addReg(MSP430::SP) in emitPrologue()
175 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
176 .addReg(MSP430::SP) in emitPrologue()
226 unsigned DwarfStackPtr = TRI->getDwarfRegNum(MSP430::SP, true); in emitEpilogue()
263 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::SP) in emitEpilogue()
269 .addReg(MSP430::SP) in emitEpilogue()
280 .addReg(MSP430::SP) in emitEpilogue()
382 .addReg(MSP430::SP) in eliminateCallFramePseudoInstr()
390 MSP430::SP) in eliminateCallFramePseudoInstr()
391 .addReg(MSP430::SP) in eliminateCallFramePseudoInstr()
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/freebsd-14.2/contrib/ntp/scripts/stats/
H A DREADME.timecodes19 <SP> ASCII space (hex 20)
29 In the following uppercase letters, punctuation marks and spaces <SP>
31 Special characters other than <LF>, <CR> and <SP> are preceded by ^.
39 i = synchronization flag (<SP> = in synch, ? = out synch)
44 Note: alarm condition is indicated by other than <SP> at A, which
57 i = synchronization flag (<SP> = in synch, ? = out synch)
64 d = standard/daylight time indicator (<SP> standard, D daylight)
69 other than <SP> at Q, with time since last lock indicated by the
83 q = quality/alarm indicator (<SP> = locked, ? = alarm)
131 a = AM/PM indicator (A = AM, P = PM, <SP> - 24-hour format)
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DEntryExitInstrumenter.cpp105 if (auto SP = F.getSubprogram()) in runOnFunction() local
106 DL = DILocation::get(SP->getContext(), SP->getScopeLine(), 0, SP); in runOnFunction()
126 else if (auto SP = F.getSubprogram()) in runOnFunction() local
127 DL = DILocation::get(SP->getContext(), 0, 0, SP); in runOnFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfUnit.cpp430 assert(SP); in addSourceLine()
432 addSourceLine(Die, SP->getLine(), SP->getFile()); in addSourceLine()
1178 if (SP->isDefinition()) in getOrCreateSubprogramDIE()
1267 if (SP->isObjCDirect()) in applySubprogramAttributes()
1309 if (SP->isArtificial()) in applySubprogramAttributes()
1316 if (SP->isOptimized()) in applySubprogramAttributes()
1329 if (SP->isNoReturn()) in applySubprogramAttributes()
1334 if (SP->isExplicit()) in applySubprogramAttributes()
1339 if (SP->isPure()) in applySubprogramAttributes()
1341 if (SP->isElemental()) in applySubprogramAttributes()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp49 using namespace SP;
186 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
187 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
188 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
189 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
190 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
191 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
192 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
193 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
764 case SP::SET: in MatchAndEmitInstruction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h74 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
78 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
82 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
119 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
124 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
H A DMips16InstrInfo.cpp210 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, in makeFrame() argument
240 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, in restoreFrame() argument
261 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1); in restoreFrame()
290 MIB2.addReg(Mips::SP, RegState::Kill); in adjustStackPtrBig()
295 Mips::SP); in adjustStackPtrBig()
300 unsigned SP, int64_t Amount, MachineBasicBlock &MBB, in adjustStackPtrBigUnrestricted() argument
306 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, in adjustStackPtr() argument
315 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I); in adjustStackPtr()
400 if (FrameReg == Mips::SP) { in loadImmediate()
414 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false); in loadImmediate()
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