34 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}  in SparcRegisterInfo()
56   Reserved.set(SP::G1);  in getReservedRegs()
60     Reserved.set(SP::G2);  in getReservedRegs()
61     Reserved.set(SP::G3);  in getReservedRegs()
62     Reserved.set(SP::G4);  in getReservedRegs()
66     Reserved.set(SP::G5);  in getReservedRegs()
68   Reserved.set(SP::O6);  in getReservedRegs()
69   Reserved.set(SP::I6);  in getReservedRegs()
70   Reserved.set(SP::I7);  in getReservedRegs()
71   Reserved.set(SP::G0);  in getReservedRegs()
72   Reserved.set(SP::G6);  in getReservedRegs()
73   Reserved.set(SP::G7);  in getReservedRegs()
77   Reserved.set(SP::G0_G1);  in getReservedRegs()
79     Reserved.set(SP::G2_G3);  in getReservedRegs()
81     Reserved.set(SP::G4_G5);  in getReservedRegs()
83   Reserved.set(SP::O6_O7);  in getReservedRegs()
84   Reserved.set(SP::I6_I7);  in getReservedRegs()
85   Reserved.set(SP::G6_G7);  in getReservedRegs()
90       for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)  in getReservedRegs()
97     Reserved.set(SP::ASR1 + n);  in getReservedRegs()
99   for (TargetRegisterClass::iterator i = SP::IntRegsRegClass.begin();  in getReservedRegs()
100        i != SP::IntRegsRegClass.end(); ++i) {  in getReservedRegs()
118   return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;  in getPointerRegClass()
142     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)  in replaceFI()
147     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)  in replaceFI()
150     MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);  in replaceFI()
160   BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)  in replaceFI()
162   BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)  in replaceFI()
163     .addReg(SP::G1).addImm(LOX10(Offset));  in replaceFI()
165   BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)  in replaceFI()
168   MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);  in replaceFI()
193     if (MI.getOpcode() == SP::STQFri) {  in eliminateFrameIndex()
196       Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);  in eliminateFrameIndex()
197       Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);  in eliminateFrameIndex()
199         BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))  in eliminateFrameIndex()
202       MI.setDesc(TII.get(SP::STDFri));  in eliminateFrameIndex()
205     } else if (MI.getOpcode() == SP::LDQFri) {  in eliminateFrameIndex()
208       Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);  in eliminateFrameIndex()
209       Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);  in eliminateFrameIndex()
211         BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)  in eliminateFrameIndex()
215       MI.setDesc(TII.get(SP::LDDFri));  in eliminateFrameIndex()
227   return SP::I6;  in getFrameRegister()