Home
last modified time | relevance | path

Searched refs:SOffset (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h162 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
165 SDValue &SOffset, SDValue &Offset) const;
167 SDValue &VAddr, SDValue &SOffset,
174 bool SelectBUFSOffset(SDValue Addr, SDValue &SOffset) const;
193 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
197 bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
200 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
204 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &SOffset) const;
205 bool SelectSMRDSgprImm(SDValue Addr, SDValue &SBase, SDValue &SOffset,
209 bool SelectSMRDBufferSgprImm(SDValue N, SDValue &SOffset,
H A DAMDGPUISelDAGToDAG.cpp1328 SOffset = Subtarget->hasRestrictedSOffset() in SelectMUBUF()
1394 SOffset = in SelectMUBUF()
1536 SOffset = Addr; in SelectMUBUFScratchOffset()
1550 SOffset = Addr.getOperand(0); in SelectMUBUFScratchOffset()
1597 SOffset = ByteOffsetNode; in SelectBUFSOffset()
1989 assert((!SOffset || !Offset) && in SelectSMRDOffset()
1994 if (!SOffset) in SelectSMRDOffset()
1998 *SOffset = ByteOffsetNode; in SelectSMRDOffset()
2035 if (SOffset) { in SelectSMRDOffset()
2037 *SOffset = SDValue( in SelectSMRDOffset()
[all …]
H A DAMDGPUInstructionSelector.h223 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
297 Register &SOffset, int64_t &ImmOffset) const;
302 Register &RSrcReg, Register &SOffset,
306 Register &SOffset, int64_t &Offset) const;
H A DSIRegisterInfo.cpp907 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1338 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1410 SOffset = MCRegister(); in buildSpillLoadStore()
1425 SOffset = Reg; in buildSpillLoadStore()
1432 SOffset = Register(); in buildSpillLoadStore()
1434 if (!SOffset) { in buildSpillLoadStore()
1463 SOffset = ScratchOffsetReg; in buildSpillLoadStore()
1475 if (!UseVGPROffset && !SOffset) in buildSpillLoadStore()
1648 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1714 .addReg(SOffset) in buildSpillLoadStore()
[all …]
H A DAMDGPUInstructionSelector.cpp4240 if (SOffset && Offset) { in selectSmrdOffset()
4280 *SOffset = OffsetReg; in selectSmrdOffset()
4322 Register Base, SOffset; in selectSmrdSgpr() local
4332 Register Base, SOffset; in selectSmrdSgprImm() local
5158 .addDef(SOffset) in splitIllegalMUBUFOffset()
5243 Register SOffset; in selectMUBUFAddr64() local
5259 if (SOffset) in selectMUBUFAddr64()
5278 Register SOffset; in selectMUBUFOffset() local
5289 if (SOffset) in selectMUBUFOffset()
5358 Register SOffset; in selectSMRDBufferSgprImm() local
[all …]
H A DAMDGPURegisterBankInfo.cpp1255 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1256 if (TII->splitMUBUFOffset(*Imm, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1258 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1263 return SOffset + ImmOffset; in setBufferOffsets()
1273 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1275 TII->splitMUBUFOffset(Offset, SOffset, ImmOffset, Alignment)) { in setBufferOffsets()
1278 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1285 if (SOffset == 0) { in setBufferOffsets()
1363 Register SOffset; in applyMappingSBufferLoad() local
1368 SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
[all …]
H A DSIISelLowering.cpp8333 return SOffset; in selectSOffset()
8351 SOffset, // soffset in lowerRawBufferAtomicIntrin()
8385 SOffset, // soffset in lowerStructBufferAtomicIntrin()
8547 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8572 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8622 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8649 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8882 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
8905 SOffset, // soffset in LowerINTRINSIC_W_CHAIN()
9848 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
[all …]
H A DSILoadStoreOptimizer.cpp97 bool SOffset = false; member
629 Result.SOffset = true; in getRegs()
657 Result.SOffset = true; in getRegs()
670 Result.SOffset = true; in getRegs()
793 if (Regs.SOffset) in setMI()
H A DAMDGPULegalizerInfo.cpp5635 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
5673 .addUse(SOffset) // soffset in legalizeBufferStore()
5688 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad() argument
5697 .addUse(SOffset) // soffset in buildBufferLoad()
5746 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
5808 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
5824 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
5831 buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, in legalizeBufferLoad()
5841 buildBufferLoad(Opc, Dst, RSrc, VIndex, VOffset, SOffset, ImmOffset, Format, in legalizeBufferLoad()
5979 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
[all …]
H A DGCNHazardRecognizer.cpp830 const MachineOperand *SOffset = in createsVALUHazard() local
835 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DBUFInstructions.td162 dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset),
165 dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset,
412 dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
413 …dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset, CPol_0:$cpol, i1imm…
689 dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
690 dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset));
H A DSIInstrInfo.cpp446 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
448 if (SOffset) { in getMemOperandsWithOffsetWidth()
449 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
450 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
452 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
6738 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
6753 .add(*SOffset) in legalizeOperands()
6777 .add(*SOffset) in legalizeOperands()
8924 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, in splitMUBUFOffset() argument
8965 SOffset = Overflow; in splitMUBUFOffset()
H A DSIInstrInfo.h1309 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPU.td858 "Has restricted SOffset (immediate not supported)."
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp722 unsigned SOffset = 0; in getMachineOpValue() local
739 ++SOffset; in getMachineOpValue()
765 : SOffset; in getMachineOpValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp332 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
334 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5617 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
5675 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
5717 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
5719 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
5721 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()