4223                                                  Register *SOffset,  in selectSmrdOffset()  argument
4240   if (SOffset && Offset) {  in selectSmrdOffset()
4248           *SOffset = OffsetReg;  in selectSmrdOffset()
4264   if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) &&  in selectSmrdOffset()
4271     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
4272     BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset)  in selectSmrdOffset()
4277   if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) {  in selectSmrdOffset()
4280       *SOffset = OffsetReg;  in selectSmrdOffset()
4322   Register Base, SOffset;  in selectSmrdSgpr()  local
4323   if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr))  in selectSmrdSgpr()
4327            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};  in selectSmrdSgpr()
4332   Register Base, SOffset;  in selectSmrdSgprImm()  local
4334   if (!selectSmrdOffset(Root, Base, &SOffset, &Offset))  in selectSmrdSgprImm()
4338            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },  in selectSmrdSgprImm()
5151   MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const {  in splitIllegalMUBUFOffset()  argument
5156   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()
5158     .addDef(SOffset)  in splitIllegalMUBUFOffset()
5165   Register &SOffset, int64_t &Offset) const {  in selectMUBUFAddr64Impl()  argument
5210   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFAddr64Impl()
5215   MachineOperand &Root, Register &RSrcReg, Register &SOffset,  in selectMUBUFOffsetImpl()  argument
5235   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFOffsetImpl()
5243   Register SOffset;  in selectMUBUFAddr64()  local
5246   if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))  in selectMUBUFAddr64()
5259         if (SOffset)  in selectMUBUFAddr64()
5260           MIB.addReg(SOffset);  in selectMUBUFAddr64()
5278   Register SOffset;  in selectMUBUFOffset()  local
5281   if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset))  in selectMUBUFOffset()
5289         if (SOffset)  in selectMUBUFOffset()
5290           MIB.addReg(SOffset);  in selectMUBUFOffset()
5306   Register SOffset = Root.getReg();  in selectBUFSOffset()  local
5308   if (STI.hasRestrictedSOffset() && mi_match(SOffset, *MRI, m_ZeroInt()))  in selectBUFSOffset()
5309     SOffset = AMDGPU::SGPR_NULL;  in selectBUFSOffset()
5311   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};  in selectBUFSOffset()
5358   Register SOffset;  in selectSMRDBufferSgprImm()  local
5360   std::tie(SOffset, Offset) = AMDGPU::getBaseWithConstantOffset(  in selectSMRDBufferSgprImm()
5362   if (!SOffset)  in selectSMRDBufferSgprImm()
5370   assert(MRI->getType(SOffset) == LLT::scalar(32));  in selectSMRDBufferSgprImm()
5371   return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },  in selectSMRDBufferSgprImm()