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Searched refs:SINT_TO_FP (Results 1 – 25 of 39) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp684 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
770 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
772 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
774 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
776 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
778 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
780 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
782 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
784 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
786 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp174 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
179 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
305 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
458 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addMVEVectorTypes()
469 setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
5986 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
5988 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
6006 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
9693 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
10567 case ISD::SINT_TO_FP: in LowerOperation()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2216 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
2217 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
2329 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
2330 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
2331 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
2332 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
2333 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
2334 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
2335 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
2336 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp943 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
2469 ISD::SINT_TO_FP, in X86TargetLowering()
18829 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP_AVX512DQ()
18871 assert((Op.getOpcode() == ISD::SINT_TO_FP || in LowerI64IntToFP16()
18908 case ISD::SINT_TO_FP: in useVectorCast()
28814 if (Op->getOpcode() == ISD::SINT_TO_FP || in LowerWin64_INT128_TO_FP()
32623 case ISD::SINT_TO_FP: in ReplaceNodeResults()
53589 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
53605 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P); in combineUIntToFP()
55596 if (InOpcode == ISD::SINT_TO_FP && in combineEXTRACT_SUBVECTOR()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2333 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
2334 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
2335 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
2341 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
2342 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
2343 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
2349 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
2350 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
2356 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
2365 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp532 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
533 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
534 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
1303 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1399 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1912 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
6253 case ISD::SINT_TO_FP: in LowerOperation()
17410 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
17455 bool IsSigned = Opc == ISD::SINT_TO_FP; in performFDivCombine()
23877 case ISD::SINT_TO_FP: in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def58 DAG_INSTRUCTION(SIToFP, 1, 1, experimental_constrained_sitofp, SINT_TO_FP)
H A DVPIntrinsics.def467 HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, SINT_TO_FP, 1)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h790 SINT_TO_FP, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp254 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
327 setOperationAction(ISD::SINT_TO_FP, T, Custom); in initializeHVXLowering()
428 setOperationAction(ISD::SINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2302 assert(Op.getOpcode() == ISD::SINT_TO_FP || in LowerHvxIntToFp()
2677 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2687 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2828 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
2862 bool Signed = Opc == ISD::SINT_TO_FP; in ExpandHvxIntToFp()
3154 case ISD::SINT_TO_FP: in LowerHvxOperation()
3236 case ISD::SINT_TO_FP: in LowerHvxOperation()
[all …]
H A DHexagonISelLowering.cpp1781 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1782 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1783 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp458 case ISD::SINT_TO_FP: in LegalizeOp()
686 case ISD::SINT_TO_FP: in Promote()
1603 if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) == in ExpandUINT_TO_FLOAT()
1666 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI); in ExpandUINT_TO_FLOAT()
1668 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO); in ExpandUINT_TO_FLOAT()
H A DLegalizeDAG.cpp1025 case ISD::SINT_TO_FP: in LegalizeOp()
2623 Node->getOpcode() == ISD::SINT_TO_FP); in ExpandLegalINT_TO_FP()
2752 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or); in ExpandLegalINT_TO_FP()
2754 Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2777 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2842 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP || in PromoteLegalINT_TO_FP()
3335 case ISD::SINT_TO_FP: in ExpandNode()
4662 case ISD::SINT_TO_FP: in ConvertNodeToLibcall()
4666 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP || in ConvertNodeToLibcall()
4938 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp144 case ISD::SINT_TO_FP: in SoftenFloatResult()
853 bool Signed = N->getOpcode() == ISD::SINT_TO_FP || in SoftenFloatRes_XINT_TO_FP()
1361 case ISD::SINT_TO_FP: in ExpandFloatResult()
1773 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP || in ExpandFloatRes_XINT_TO_FP()
2449 case ISD::SINT_TO_FP: in PromoteFloatResult()
2854 case ISD::SINT_TO_FP: in SoftPromoteHalfResult()
H A DSelectionDAGDumper.cpp365 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
H A DFastISel.cpp310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1858 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
H A DLegalizeVectorTypes.cpp112 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
684 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
1114 case ISD::SINT_TO_FP: in SplitVectorResult()
3012 case ISD::SINT_TO_FP: in SplitVectorOperand()
4248 case ISD::SINT_TO_FP: in WidenVectorResult()
6076 case ISD::SINT_TO_FP: in WidenVectorOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp261 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
283 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
532 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
8508 if (UI->getOpcode() != ISD::SINT_TO_FP && in directMoveIsProfitable()
8521 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in convertIntToFP()
8557 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FPDirectMove()
8647 bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || in LowerINT_TO_FP()
14864 if (FirstInput.getOpcode() != ISD::SINT_TO_FP && in DAGCombineBuildVector()
14906 assert((N->getOpcode() == ISD::SINT_TO_FP || in combineFPToIntToFP()
14932 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in combineFPToIntToFP()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp175 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
261 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1977 case ISD::SINT_TO_FP: in LowerConvertLow()
2492 N->getOpcode() == ISD::SINT_TO_FP); in performVectorExtendToFPCombine()
2878 case ISD::SINT_TO_FP: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1690 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1692 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3263 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3637 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3644 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp438 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
462 ISD::ROTR, ISD::SUB, ISD::SINT_TO_FP, in AMDGPUTargetLowering()
1359 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1887 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
3252 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
3289 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3360 return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext); in LowerSINT_TO_FP()
3365 SDValue ToF32 = DAG.getNode(ISD::SINT_TO_FP, SL, MVT::f32, Src); in LowerSINT_TO_FP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in LoongArchTargetLowering()
269 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
315 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
405 case ISD::SINT_TO_FP: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp887 case ISD::SINT_TO_FP: in getCastInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp525 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
698 ISD::SINT_TO_FP, ISD::UINT_TO_FP}, in NVPTXTargetLowering()
781 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2711 case ISD::SINT_TO_FP: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp274 setOperationAction(ISD::SINT_TO_FP, MVT::i128, LibCall); in SystemZTargetLowering()
460 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
461 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
480 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
481 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
713 ISD::SINT_TO_FP, in SystemZTargetLowering()
7684 case ISD::SINT_TO_FP: in PerformDAGCombine()

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