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Searched refs:SETCC (Results 1 – 25 of 62) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3156 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } }, in getCmpSelInstrCost()
3167 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3168 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3169 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3170 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3177 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3178 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3179 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3180 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3182 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
[all …]
H A DX86ISelLowering.cpp2473 ISD::SETCC, in X86TargetLowering()
31923 case ISD::SETCC: in LowerOperation()
33154 NODE_NAME_CASE(SETCC) in getTargetNodeName()
36558 case X86ISD::SETCC: in computeKnownBitsForTargetNode()
42406 case ISD::SETCC: in checkBitcastSrcVectorSize()
42444 case ISD::SETCC: in adjustBitcastSrcVectorSSE1()
42474 case ISD::SETCC: in signExtendBitcastSrcVector()
45539 case X86ISD::SETCC: in checkBoolTestSetCCCombine()
48041 (N0.getOpcode() == ISD::SETCC && N1.getOpcode() == ISD::SETCC))) in convertIntLogicToFPLogic()
53751 case X86ISD::SETCC: in needCarryOrOverflowFlag()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.h185 static inline bool IsSETCC(unsigned SETCC) { in IsSETCC() argument
186 switch (SETCC) { in IsSETCC()
H A DM68kISelLowering.cpp129 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
1388 case ISD::SETCC: in LowerOperation()
1669 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
2171 if (Op0.getOpcode() == M68kISD::SETCC) { in LowerSETCC()
2203 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2267 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2276 if (Cond.getOpcode() == M68kISD::SETCC && in LowerSELECT()
2458 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
3548 if (Carry.getOpcode() == M68kISD::SETCC || in combineCarryThroughADD()
3635 case M68kISD::SETCC: in PerformDAGCombine()
[all …]
H A DM68kISelLowering.h53 SETCC, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h41 SETCC, enumerator
H A DLanaiISelLowering.cpp88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
190 case ISD::SETCC: in LowerOperation()
982 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue); in LowerSETCC()
1106 case LanaiISD::SETCC: in getTargetNodeName()
1496 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h54 SETCC, enumerator
H A DMSP430ISelLowering.cpp92 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
348 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
1378 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; in getTargetNodeName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def119 ADD_VVP_OP(VVP_SETCC, SETCC)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def65 // Both of these match to FCmp / SETCC.
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h750 SETCC, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp516 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
705 case ISD::SETCC: in ScalarizeVectorOperand()
1032 case ISD::SETCC: in SplitVectorResult()
1953 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_LOAD()
2028 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_STRIDED_LOAD()
2108 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MLOAD()
2287 if (N->getOpcode() == ISD::SETCC) { in SplitVecRes_SETCC()
3457 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) { in SplitVecOp_VP_STORE()
3535 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) in SplitVecOp_VP_STRIDED_STORE()
3933 if (N->getOpcode() == ISD::SETCC) { in SplitVecOp_VSETCC()
[all …]
H A DLegalizeVectorOps.cpp483 case ISD::SETCC: { in LegalizeOp()
718 case ISD::SETCC: in Promote()
931 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
952 case ISD::SETCC: in Expand()
1749 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
1920 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
H A DDAGCombiner.cpp1097 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1361 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC && in reassociateOpsCommutative()
2396 if (N.getOpcode() != ISD::SETCC || in isTruncateOf()
6156 if (LHS->getOpcode() != ISD::SETCC || RHS->getOpcode() != ISD::SETCC || in foldAndOrOfSETCC()
9449 case ISD::SETCC: in visitXOR()
11635 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
12175 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
13248 if (N0.getOpcode() != ISD::SETCC) in foldSextSetcc()
13831 if (N0.getOpcode() == ISD::SETCC) { in visitZERO_EXTEND()
18011 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { in rebuildSetCC()
[all …]
H A DLegalizeDAG.cpp1060 case ISD::SETCC: in LegalizeOp()
1069 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2 in LegalizeOp()
3934 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3994 if (Tmp2.getOpcode() == ISD::SETCC && in ExpandNode()
4015 case ISD::SETCC: in ExpandNode()
4106 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags()); in ExpandNode()
4939 Node->getOpcode() == ISD::SETCC || in PromoteNode()
5204 case ISD::SETCC: in PromoteNode()
5233 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1, in PromoteNode()
H A DLegalizeFloatTypes.cpp941 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; in SoftenFloatOperand()
1129 NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS, in SoftenFloatOp_SETCC()
1910 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; in ExpandFloatOperand()
2244 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break; in PromoteFloatOperand()
3143 case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break; in SoftPromoteHalfOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp169 setOperationAction(ISD::SETCC, P, Custom); in initializeHVXLowering()
305 setOperationAction(ISD::SETCC, T, Custom); in initializeHVXLowering()
376 setOperationAction(ISD::SETCC, BoolW, Custom); in initializeHVXLowering()
420 setOperationAction(ISD::SETCC, VecTy, Custom); in initializeHVXLowering()
434 setOperationAction(ISD::SETCC, BoolTy, Custom); in initializeHVXLowering()
3129 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC()
3185 case ISD::SETCC: in LowerHvxOperation()
3226 case ISD::SETCC: in LowerHvxOperation()
3376 case ISD::SETCC: in LowerHvxOperationWrapper()
3442 case ISD::SETCC: in ReplaceHvxNodeResults()
H A DHexagonISelLowering.cpp1515 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1516 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1517 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1518 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1756 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
3375 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp102 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
124 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
239 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
243 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
248 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
286 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
354 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
391 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
1043 case ISD::SETCC: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp442 case ISD::SETCC: in NVPTXTargetLowering()
492 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
493 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
501 setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
502 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
503 if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote) in NVPTXTargetLowering()
504 AddPromotedToType(ISD::SETCC, MVT::bf16, MVT::f32); in NVPTXTargetLowering()
525 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
732 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
5674 case ISD::SETCC: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp113 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
114 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
116 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
1012 case ISD::SETCC: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h429 SETCC, enumerator
H A DR600ISelLowering.cpp97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
109 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
745 ISD::SETCC, in lowerFP_TO_UINT()
755 ISD::SETCC, in lowerFP_TO_SINT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp994 setTargetDAGCombine(ISD::SETCC); in AArch64TargetLowering()
3326 if (Opcode == ISD::SETCC) { in canEmitConjunction()
3387 if (Opcode == ISD::SETCC) { in emitConjunctionRec()
6122 case ISD::SETCC: in LowerOperation()
9342 if (N->getOpcode() != ISD::SETCC) in performOrXorChainCombine()
9815 if (CCVal.getOpcode() == ISD::SETCC) { in LowerSELECT()
17961 if ((N.getOpcode() == ISD::SETCC) || in isPredicateCCSettingOp()
18582 if (Op.getOpcode() == ISD::SETCC) { in isSetCC()
22814 if (N0.getOpcode() != ISD::SETCC || in performVSelectCombine()
22845 if (N0.getOpcode() != ISD::SETCC) in performSelectCombine()
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