| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 351 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
354 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
356 "# SELECT_CC PSEUDO!",
1193 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1196 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1199 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1201 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1203 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1207 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1291 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 107 setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom); in R600TargetLowering()
202 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
410 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
853 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
910 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
934 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
936 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1745 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1753 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1836 case ISD::SELECT_CC: { in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.h | 28 SELECT_CC, enumerator
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| H A D | BPFISelLowering.cpp | 119 setOperationAction(ISD::SELECT_CC, VT, Custom); in BPFTargetLowering()
311 case ISD::SELECT_CC: in LowerOperation()
671 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); in LowerSELECT_CC()
682 case BPFISD::SELECT_CC: in getTargetNodeName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.h | 38 SELECT_CC, enumerator
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| H A D | LanaiISelLowering.cpp | 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in LanaiTargetLowering()
188 case ISD::SELECT_CC: in LowerOperation()
1000 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC, in LowerSELECT_CC()
1104 case LanaiISD::SELECT_CC: in getTargetNodeName()
1500 case LanaiISD::SELECT_CC: in computeKnownBitsForTargetNode()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 64 SELECT_CC, enumerator
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| H A D | MSP430ISelLowering.cpp | 96 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
350 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1208 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops); in LowerSETCC()
1226 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops); in LowerSELECT_CC()
1379 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 75 SELECT_CC enumerator
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| H A D | AVRISelLowering.cpp | 109 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in AVRTargetLowering()
110 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in AVRTargetLowering()
111 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in AVRTargetLowering()
112 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AVRTargetLowering()
269 NODE(SELECT_CC); in getTargetNodeName()
913 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); in LowerSELECT_CC()
930 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); in LowerSETCC()
1010 case ISD::SELECT_CC: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 140 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
823 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
938 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
1290 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1907 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
2243 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; in PromoteFloatOperand()
2332 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatOp_SELECT_CC()
2447 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; in PromoteFloatResult()
2707 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteFloatRes_SELECT_CC()
2853 case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break; in SoftPromoteHalfResult()
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| H A D | LegalizeTypesGeneric.cpp | 561 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
563 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
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| H A D | LegalizeDAG.cpp | 1057 case ISD::SELECT_CC: in LegalizeOp()
1065 unsigned CCOperand = Opc == ISD::SELECT_CC ? 4 in LegalizeOp()
1080 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
4080 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
4087 case ISD::SELECT_CC: { in ExpandNode()
4150 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), in ExpandNode()
4155 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
4950 Node->getOpcode() == ISD::SELECT_CC) in PromoteNode()
5167 case ISD::SELECT_CC: { in PromoteNode()
5191 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, NVT, {Tmp1, Tmp2, Tmp3, Tmp4, Cond}, in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 376 case ISD::SELECT_CC: in LegalizeOp()
926 case ISD::SELECT_CC: { in Expand()
1769 DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS, in ExpandSETCC()
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| H A D | SelectionDAGDumper.cpp | 300 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 742 SELECT_CC, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 145 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in ARCTargetLowering()
792 case ISD::SELECT_CC: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 918 setTargetDAGCombine(ISD::SELECT_CC); in VETargetLowering()
2832 assert(N->getOpcode() == ISD::SELECT_CC && in combineSelectCC()
2929 case ISD::SELECT_CC: in isI32Insn()
2976 if (User->getOpcode() == ISD::SELECT_CC || in isI32InsnAllUses()
3004 if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC && in combineTRUNCATE()
3036 case ISD::SELECT_CC: in PerformDAGCombine()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 503 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
504 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
831 setOperationAction(ISD::SELECT_CC, VT, Promote); in PPCTargetLowering()
832 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
13881 N->getOpcode() == ISD::SELECT_CC) { in DAGCombineTruncBoolExt()
14097 case ISD::SELECT_CC: C = 2; break; in DAGCombineTruncBoolExt()
14164 N->getOperand(0).getOpcode() != ISD::SELECT_CC) in DAGCombineExtBoolTrunc()
14324 case ISD::SELECT_CC: C = 2; break; in DAGCombineExtBoolTrunc()
14342 PromOp.getOpcode() == ISD::SELECT_CC) { in DAGCombineExtBoolTrunc()
14373 PromOp.getOpcode() == ISD::SELECT_CC) { in DAGCombineExtBoolTrunc()
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| H A D | PPCISelDAGToDAG.cpp | 4019 Compare.getOpcode() == ISD::SELECT_CC) && in getSETCCInGPR()
4031 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2; in getSETCCInGPR()
4693 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here."); in mayUseP9Setb()
4714 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ))) in mayUseP9Setb()
4717 SDValue SetOrSelCC = FalseRes.getOpcode() == ISD::SELECT_CC in mayUseP9Setb()
4720 bool InnerIsSel = SetOrSelCC.getOpcode() == ISD::SELECT_CC; in mayUseP9Setb()
4722 SetOrSelCC.getOpcode() != ISD::SELECT_CC) in mayUseP9Setb()
5837 case ISD::SELECT_CC: { in Select()
6385 if (O.getOpcode() != ISD::SELECT_CC) in combineToCMPB()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1731 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1732 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1733 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1734 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1751 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
3271 case ISD::SELECT_CC: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 69 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in CSKYTargetLowering()
129 setOperationAction(ISD::SELECT_CC, VT, Expand); in CSKYTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 126 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in MipsSETargetLowering()
241 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsSETargetLowering()
245 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in MipsSETargetLowering()
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in MipsSETargetLowering()
288 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsSETargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 43 SELECT_CC, enumerator
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| H A D | RISCVISelLowering.cpp | 248 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
250 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in RISCVTargetLowering()
850 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
984 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
6477 case ISD::SELECT_CC: { in LowerOperation()
12372 Slct.getOpcode() != RISCVISD::SELECT_CC) || in combineSelectAndUse()
12401 if (Slct.getOpcode() == RISCVISD::SELECT_CC) in combineSelectAndUse()
15394 case RISCVISD::SELECT_CC: { in PerformDAGCombine()
16288 case RISCVISD::SELECT_CC: { in computeKnownBitsForTargetNode()
16418 case RISCVISD::SELECT_CC: { in ComputeNumSignBitsForTargetNode()
[all …]
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