Lines Matching refs:SELECT_CC
248 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
250 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in RISCVTargetLowering()
462 setOperationAction(ISD::SELECT_CC, MVT::bf16, Expand); in RISCVTargetLowering()
491 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand); in RISCVTargetLowering()
523 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in RISCVTargetLowering()
565 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in RISCVTargetLowering()
734 {ISD::SELECT_CC, ISD::VSELECT, ISD::VP_MERGE, ISD::VP_SELECT}, VT, in RISCVTargetLowering()
850 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
984 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
1035 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
1194 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
1307 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
6477 case ISD::SELECT_CC: { in LowerOperation()
7276 return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops); in lowerSELECT()
7333 return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops); in lowerSELECT()
12372 Slct.getOpcode() != RISCVISD::SELECT_CC) || in combineSelectAndUse()
12381 unsigned OpOffset = Slct.getOpcode() == RISCVISD::SELECT_CC ? 2 : 0; in combineSelectAndUse()
12401 if (Slct.getOpcode() == RISCVISD::SELECT_CC) in combineSelectAndUse()
12402 return DAG.getNode(RISCVISD::SELECT_CC, SDLoc(N), VT, in combineSelectAndUse()
15394 case RISCVISD::SELECT_CC: { in PerformDAGCombine()
15437 return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
15490 SDValue NewSel = DAG.getNode(RISCVISD::SELECT_CC, DL, VT, LHS, RHS, CC, in PerformDAGCombine()
16288 case RISCVISD::SELECT_CC: { in computeKnownBitsForTargetNode()
16418 case RISCVISD::SELECT_CC: { in ComputeNumSignBitsForTargetNode()
18805 NODE_NAME_CASE(SELECT_CC) in getTargetNodeName()