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Searched refs:SDep (Results 1 – 25 of 35) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUExportClustering.cpp69 for (const SDep &Pred : SUb->Preds) { in buildCluster()
72 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial)); in buildCluster()
76 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier)); in buildCluster()
78 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)); in buildCluster()
83 SmallVector<SDep, 2> ToAdd, ToRemove; in removeExportDependencies()
85 for (const SDep &Pred : SU.Preds) { in removeExportDependencies()
97 ToAdd.push_back(SDep(ExportPredSU, SDep::Barrier)); in removeExportDependencies()
102 for (SDep Pred : ToRemove) in removeExportDependencies()
104 for (SDep Pred : ToAdd) in removeExportDependencies()
128 SmallVector<SDep, 4> Succs(SU.Succs); in apply()
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H A DSIMachineScheduler.cpp424 for (SDep& Succ : SU->Succs) { in undoSchedule()
465 for (SDep& Succ : SU->Succs) { in releaseSuccessors()
497 for (SDep& Succ : SU->Succs) { in nodeScheduled()
801 for (SDep& PredDep : SU->Preds) { in colorComputeReservedDependencies()
843 for (SDep& SuccDep : SU->Succs) { in colorComputeReservedDependencies()
925 for (SDep& SuccDep : SU->Succs) { in colorEndsAccordingToDependencies()
995 for (SDep& SuccDep : SU->Succs) { in colorMergeConstantLoadsNextGroup()
1016 for (SDep& SuccDep : SU->Succs) { in colorMergeIfPossibleNextGroup()
1037 for (SDep& SuccDep : SU->Succs) { in colorMergeIfPossibleNextGroupOnlyForReserved()
1069 for (SDep& SuccDep : SU->Succs) { in colorMergeIfPossibleSmallGroupsToNextGroup()
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H A DAMDGPUSubtarget.cpp853 int UseOpIdx, SDep &Dep) const { in adjustSchedDependency()
854 if (Dep.getKind() != SDep::Kind::Data || !Dep.getReg() || in adjustSchedDependency()
930 if (DAG->addEdge(SU, SDep(From, SDep::Artificial))) in linkSALUChain()
933 for (SDep &SI : From->Succs) { in linkSALUChain()
937 DAG->addEdge(SUv, SDep(SU, SDep::Artificial)); in linkSALUChain()
940 for (SDep &SI : SU->Succs) { in linkSALUChain()
H A DGCNMinRegStrategy.cpp88 for (auto SDep : SU->Succs) { in getReadySuccessors() local
90 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
181 S.getKind() != SDep::Data) in bumpPredsPriority()
H A DGCNILPSched.cpp64 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
108 for (const SDep &Succ : SU->Succs) { in closestSucc()
123 for (const SDep &Pred : SU->Preds) { in calcMaxScratches()
H A DR600Packetizer.cpp190 const SDep &Dep = SUJ->Succs[i]; in isLegalToPacketizeTogether()
193 if (Dep.getKind() == SDep::Anti) in isLegalToPacketizeTogether()
195 if (Dep.getKind() == SDep::Output) in isLegalToPacketizeTogether()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp34 static bool isHazard(const SDep &Dep) { in isHazard()
35 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output; in isHazard()
39 for (const SDep &SI : SU.Preds) in getPredClusterSU()
57 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
61 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
70 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) in fuseInstructionPair()
82 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
86 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
106 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); in fuseInstructionPair()
118 DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial)); in fuseInstructionPair()
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H A DScheduleDAG.cpp108 for (SDep &PredDep : Preds) { in addPred()
119 SDep ForwardD = PredDep; in addPred()
133 SDep P = D; in addPred()
137 if (D.getKind() == SDep::Data) { in addPred()
174 void SUnit::removePred(const SDep &D) { in removePred()
180 SDep P = D; in removePred()
186 if (P.getKind() == SDep::Data) { in removePred()
225 for (SDep &SuccDep : SU->Succs) { in setDepthDirty()
240 for (SDep &PredDep : SU->Preds) { in setHeightDirty()
369 for (const SDep &Dep : SU.Preds) { in dumpNodeAll()
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H A DScheduleDAGInstrs.cpp263 SDep Dep; in addPhysRegDataDeps()
265 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
277 Dep = SDep(SU, SDep::Data, UseReg); in addPhysRegDataDeps()
310 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
322 if (Kind != SDep::Anti) { in addPhysRegDeps()
453 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
496 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
544 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
558 SDep Dep(SUa, SDep::MayAliasMem); in addChainDependency()
890 SDep Dep(SU, SDep::Artificial); in buildSchedGraph()
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H A DMachinePipeliner.cpp825 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
835 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
843 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
850 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
859 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
901 SDep Dep(SU, SDep::Anti, Reg); in updatePhiDependences()
909 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
921 SDep Dep(SU, SDep::Data, Reg); in updatePhiDependences()
930 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
1008 SDep Dep(&I, SDep::Anti, NewBase); in changeDependences()
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H A DAggressiveAntiDepBreaker.cpp259 for (const SDep &Pred : SU->Preds) { in AntiDepEdges()
260 if ((Pred.getKind() == SDep::Anti) || (Pred.getKind() == SDep::Output)) { in AntiDepEdges()
270 const SDep *Next = nullptr; in CriticalPathStep()
274 for (const SDep &Pred : SU->Preds) { in CriticalPathStep()
804 std::vector<const SDep *> Edges; in BreakAntiDependencies()
822 for (const SDep *Edge : Edges) { in BreakAntiDependencies()
825 if ((Edge->getKind() != SDep::Anti) && in BreakAntiDependencies()
826 (Edge->getKind() != SDep::Output)) continue; in BreakAntiDependencies()
865 for (const SDep &Pred : PathSU->Preds) { in BreakAntiDependencies()
874 for (const SDep &Pred : PathSU->Preds) { in BreakAntiDependencies()
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H A DCriticalAntiDepBreaker.cpp140 static const SDep *CriticalPathStep(const SUnit *SU) { in CriticalPathStep()
141 const SDep *Next = nullptr; in CriticalPathStep()
144 for (const SDep &P : SU->Preds) { in CriticalPathStep()
151 (NextDepth == PredTotalLatency && P.getKind() == SDep::Anti)) { in CriticalPathStep()
554 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { in BreakAntiDependencies()
558 if (Edge->getKind() == SDep::Anti) { in BreakAntiDependencies()
577 for (const SDep &P : CriticalPathSU->Preds) in BreakAntiDependencies()
579 ? (P.getKind() != SDep::Anti || P.getReg() != AntiDepReg) in BreakAntiDependencies()
580 : (P.getKind() == SDep::Data && in BreakAntiDependencies()
H A DLatencyPriorityQueue.cpp58 for (const SDep &P : SU->Preds) { in getSingleUnscheduledPred()
76 for (const SDep &Succ : SU->Succs) in push()
90 for (const SDep &Succ : SU->Succs) in scheduledNode()
H A DMachineScheduler.cpp699 for (SDep &Succ : SU->Succs) in releaseSuccessors()
736 for (SDep &Pred : SU->Preds) in releasePredecessors()
1856 if (!DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) in clusterNeighboringMemOps()
1868 for (const SDep &Succ : SUa->Succs) { in clusterNeighboringMemOps()
1873 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial)); in clusterNeighboringMemOps()
1882 for (const SDep &Pred : SUb->Preds) { in clusterNeighboringMemOps()
1887 DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial)); in clusterNeighboringMemOps()
2153 DAG->addEdge(GlobalSU, SDep(LU, SDep::Weak)); in constrainLocalCopy()
2158 DAG->addEdge(FirstLocalSU, SDep(GU, SDep::Weak)); in constrainLocalCopy()
3759 for (SDep &Dep : Deps) { in reschedulePhysReg()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp158 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
273 SDep ChainPred; in CopyAndMoveSuccessors()
309 for (SDep D : NodeSuccs) { in CopyAndMoveSuccessors()
326 SDep D(LoadSU, SDep::Barrier); in CopyAndMoveSuccessors()
344 for (SDep &Pred : SU->Preds) in CopyAndMoveSuccessors()
356 SDep D = Succ; in CopyAndMoveSuccessors()
392 SDep D = Succ; in InsertCopiesAndMoveSuccs()
401 SDep FromDep(SU, SDep::Data, Reg); in InsertCopiesAndMoveSuccs()
404 SDep ToDep(CopyFromSU, SDep::Data, 0); in InsertCopiesAndMoveSuccs()
607 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in ListScheduleBottomUp()
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H A DScheduleDAGRRList.cpp1112 SDep D(LoadSU, SDep::Data, 0); in TryUnfoldSU()
1190 AddPredQueued(NewSU, SDep(SU, SDep::Artificial)); in CopyAndMoveSuccessors()
1200 SDep D = Succ; in CopyAndMoveSuccessors()
1239 SDep D = Succ; in InsertCopiesAndMoveSuccs()
1248 AddPredQueued(SuccSU, SDep(CopyFromSU, SDep::Artificial)); in InsertCopiesAndMoveSuccs()
1254 SDep FromDep(SU, SDep::Data, Reg); in InsertCopiesAndMoveSuccs()
1257 SDep ToDep(CopyFromSU, SDep::Data, 0); in InsertCopiesAndMoveSuccs()
1533 AddPredQueued(TrySU, SDep(BtSU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
1587 AddPredQueued(TrySU, SDep(Copies.front(), SDep::Artificial)); in PickNodeToScheduleBottomUp()
1594 AddPredQueued(NewDef, SDep(TrySU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
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H A DResourcePriorityQueue.cpp69 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
144 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
153 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
211 for (const SDep &Pred : SU->Preds) { in getSingleUnscheduledPred()
228 for (const SDep &Succ : SU->Succs) in push()
267 for (const SDep &Succ : S->Succs) { in isResourceAvailable()
497 for (SDep &Pred : SU->Preds) { in scheduledNode()
512 for (const SDep &Succ : SU->Succs) { in scheduledNode()
H A DScheduleDAGVLIW.cpp81 void releaseSucc(SUnit *SU, const SDep &D);
109 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc()
135 for (SDep &Succ : SU->Succs) { in releaseSuccessors()
H A DScheduleDAGSDNodes.cpp510 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) in AddSchedEdges()
511 : SDep(OpSU, SDep::Data, PhysReg); in AddSchedEdges()
650 unsigned OpIdx, SDep& dep) const{ in computeOperandLatency()
655 if (dep.getKind() != SDep::Data) in computeOperandLatency()
812 for (const SDep &Pred : SU->Preds) { in EmitPhysRegCopy()
822 for (const SDep &Succ : SU->Succs) { in EmitPhysRegCopy()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h49 class SDep {
101 SDep() : Dep(nullptr, Data) {} in SDep() function
104 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep() function
123 SDep(SUnit *S, OrderKind kind) in SDep() function
385 SDep Dep(SU, SDep::Barrier); in addPredBarrier()
394 void removePred(const SDep &D);
432 for (const SDep &Pred : Preds) in isPred()
440 for (const SDep &Succ : Succs) in isSucc()
465 inline bool SDep::overlaps(const SDep &Other) const { in overlaps()
486 inline SDep::Kind SDep::getKind() const { return Dep.getInt(); } in getKind()
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H A DMachinePipeliner.h252 bool isBackedge(SUnit *Source, const SDep &Dep) { in isBackedge()
253 if (Dep.getKind() != SDep::Anti) in isBackedge()
258 bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
262 unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) { in getDistance()
265 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
341 for (const SDep &Succ : Node->Succs) { in NodeSet()
591 int earliestCycleInChain(const SDep &Dep);
595 int latestCycleInChain(const SDep &Dep);
H A DTargetSubtargetInfo.h46 class SDep; variable
238 int UseOpIdx, SDep &Dep) const {} in adjustSchedDependency()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp254 SmallVector<SDep, 4> Erase; in apply()
274 for (SDep &SI : SU.Succs) { in apply()
275 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
284 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
333 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
337 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
372 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier)); in apply()
422 SDep A(&S0, SDep::Artificial); in apply()
441 SDep &Dep) const { in adjustSchedDependency()
580 SDep T = I; in restoreLatency()
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H A DHexagonVLIWPacketizer.cpp317 if (DepType == SDep::Data) { in isCallDependent()
327 return DepType == SDep::Data || DepType == SDep::Anti || in isRegDependence()
328 DepType == SDep::Output; in isRegDependence()
378 assert(DepType == SDep::Data); in promoteToDotCur()
460 assert(DepType == SDep::Data); in promoteToDotNew()
1434 if (DepType == SDep::Data) { in isLegalToPacketizeTogether()
1446 if (DepType == SDep::Data) { in isLegalToPacketizeTogether()
1459 if (DepType == SDep::Data) { in isLegalToPacketizeTogether()
1500 DepType == SDep::Order) in isLegalToPacketizeTogether()
1506 DepType != SDep::Output) in isLegalToPacketizeTogether()
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H A DHexagonVLIWPacketizer.h119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
129 bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,

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