224   void AddPredQueued(SUnit *SU, const SDep &D) {  in AddPredQueued()
232   void AddPred(SUnit *SU, const SDep &D) {  in AddPred()
240   void RemovePred(SUnit *SU, const SDep &D) {  in RemovePred()
251   void ReleasePred(SUnit *SU, const SDep *PredEdge);
258   void CapturePred(SDep *PredEdge);
400 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {  in ReleasePred()
558   for (SDep &Pred : SU->Preds) {  in ReleasePredecessors()
772   for (SDep &Succ : SU->Succs) {  in ScheduleNodeBottomUp()
822 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {  in CapturePred()
841   for (SDep &Pred : SU->Preds) {  in UnscheduleNodeBottomUp()
1054   SmallVector<SDep, 4> ChainPreds;  in TryUnfoldSU()
1055   SmallVector<SDep, 4> ChainSuccs;  in TryUnfoldSU()
1056   SmallVector<SDep, 4> LoadPreds;  in TryUnfoldSU()
1057   SmallVector<SDep, 4> NodePreds;  in TryUnfoldSU()
1058   SmallVector<SDep, 4> NodeSuccs;  in TryUnfoldSU()
1059   for (SDep &Pred : SU->Preds) {  in TryUnfoldSU()
1067   for (SDep &Succ : SU->Succs) {  in TryUnfoldSU()
1075   for (const SDep &Pred : ChainPreds) {  in TryUnfoldSU()
1080   for (const SDep &Pred : LoadPreds) {  in TryUnfoldSU()
1085   for (const SDep &Pred : NodePreds) {  in TryUnfoldSU()
1089   for (SDep &D : NodeSuccs) {  in TryUnfoldSU()
1100   for (SDep &D : ChainSuccs) {  in TryUnfoldSU()
1112   SDep D(LoadSU, SDep::Data, 0);  in TryUnfoldSU()
1184   for (SDep &Pred : SU->Preds)  in CopyAndMoveSuccessors()
1190   AddPredQueued(NewSU, SDep(SU, SDep::Artificial));  in CopyAndMoveSuccessors()
1194   SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;  in CopyAndMoveSuccessors()
1195   for (SDep &Succ : SU->Succs) {  in CopyAndMoveSuccessors()
1200       SDep D = Succ;  in CopyAndMoveSuccessors()
1233   SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;  in InsertCopiesAndMoveSuccs()
1234   for (SDep &Succ : SU->Succs) {  in InsertCopiesAndMoveSuccs()
1239       SDep D = Succ;  in InsertCopiesAndMoveSuccs()
1248       AddPredQueued(SuccSU, SDep(CopyFromSU, SDep::Artificial));  in InsertCopiesAndMoveSuccs()
1254   SDep FromDep(SU, SDep::Data, Reg);  in InsertCopiesAndMoveSuccs()
1257   SDep ToDep(CopyFromSU, SDep::Data, 0);  in InsertCopiesAndMoveSuccs()
1357   for (SDep &Pred : SU->Preds) {  in DelayForLiveRegsBottomUp()
1533       AddPredQueued(TrySU, SDep(BtSU, SDep::Artificial));  in PickNodeToScheduleBottomUp()
1587       AddPredQueued(TrySU, SDep(Copies.front(), SDep::Artificial));  in PickNodeToScheduleBottomUp()
1594     AddPredQueued(NewDef, SDep(TrySU, SDep::Artificial));  in PickNodeToScheduleBottomUp()
1994     for (const SDep &Pred : TempSU->Preds) {  in CalcNodeSethiUllmanNumber()
2097   for (const SDep &Pred : SU->Preds) {  in HighRegPressure()
2146   for (const SDep &Pred : SU->Preds) {  in RegPressureDiff()
2189   for (const SDep &Pred : SU->Preds) {  in scheduledNode()
2271   for (const SDep &Pred : SU->Preds) {  in unscheduledNode()
2348   for (const SDep &Succ : SU->Succs) {  in closestSucc()
2366   for (const SDep &Pred : SU->Preds) {  in calcMaxScratches()
2377   for (const SDep &Pred : SU->Preds) {  in hasOnlyLiveInOpers()
2399   for (const SDep &Succ : SU->Succs) {  in hasOnlyLiveOutUses()
2436   for (const SDep &Pred : SU->Preds) {  in initVRegCycle()
2448   for (const SDep &Pred : SU->Preds) {  in resetVRegCycle()
2466   for (const SDep &Pred : SU->Preds) {  in hasVRegCycleUse()
2866   for (const SDep &Succ : SU->Succs) {  in canClobberReachingPhysRegUse()
2868     for (const SDep &SuccPred : SuccSU->Preds) {  in canClobberReachingPhysRegUse()
2975     for (const SDep &Pred : SU.Preds)  in PrescheduleNodesWithMultipleUses()
2999     for (const SDep &Pred : SU.Preds)  in PrescheduleNodesWithMultipleUses()
3021     for (const SDep &PredSucc : PredSU->Succs) {  in PrescheduleNodesWithMultipleUses()
3044       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
3090       for (const SDep &Succ : DUSU->Succs) {  in AddPseudoTwoAddrDeps()
3134           scheduleDAG->AddPredQueued(&SU, SDep(SuccSU, SDep::Artificial));  in AddPseudoTwoAddrDeps()