| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 343 case ISD::SDIV: in Select()
354 if (N->getOpcode() == ISD::SDIV) { in Select()
366 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiTargetTransformInfo.h | 106 case ISD::SDIV:
|
| H A D | LanaiISelLowering.cpp | 106 setOperationAction(ISD::SDIV, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 100 ADD_BINARY_VVP_OP_COMPACT(SDIV)
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1349 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1353 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1357 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
1361 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
1366 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1370 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1374 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1378 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2090 case ISD::SDIV: in maybeLoweredToCall()
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| H A D | ARMScheduleSwift.td | 321 (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 242 SDIV, enumerator
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 316 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
397 { ISD::SDIV, MVT::v16i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
438 { ISD::SDIV, MVT::v8i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
510 { ISD::SDIV, MVT::v4i32, { 6 } }, // pmuludq sequence in getArithmeticInstrCost()
530 { ISD::SDIV, MVT::v32i16, { 6 } }, // vpmulhw sequence in getArithmeticInstrCost()
553 { ISD::SDIV, MVT::v16i32, { 15 } }, // vpmuldq sequence in getArithmeticInstrCost()
571 { ISD::SDIV, MVT::v16i16, { 6 } }, // vpmulhw sequence in getArithmeticInstrCost()
576 { ISD::SDIV, MVT::v8i32, { 15 } }, // vpmuldq sequence in getArithmeticInstrCost()
598 { ISD::SDIV, MVT::v8i32, { 32 } }, // vpmuludq sequence in getArithmeticInstrCost()
626 { ISD::SDIV, MVT::v8i16, { 6 } }, // pmulhw sequence in getArithmeticInstrCost()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1922 case ISD::SDIV: in selectDivRem()
1924 DivOpc = Mips::SDIV; in selectDivRem()
2037 if (!selectBinaryOp(I, ISD::SDIV)) in fastSelectInstruction()
2038 return selectDivRem(I, ISD::SDIV); in fastSelectInstruction()
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| H A D | MipsSEISelLowering.cpp | 232 setOperationAction(ISD::SDIV, MVT::i32, Legal); in MipsSETargetLowering()
279 setOperationAction(ISD::SDIV, MVT::i64, Legal); in MipsSETargetLowering()
331 setOperationAction(ISD::SDIV, Ty, Legal); in addMSAIntType()
1798 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| H A D | MipsScheduleP5600.td | 192 def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 103 setOperationAction(ISD::SDIV, VT, Custom); in BPFTargetLowering()
313 case ISD::SDIV: in LowerOperation()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 2799 case ISD::SDIV: in getArithmeticInstrCost()
2846 {ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8}, in getArithmeticInstrCost()
2847 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, 5}, in getArithmeticInstrCost()
2848 {ISD::SDIV, MVT::v4i16, 5}, {ISD::SDIV, MVT::v2i32, 1}, in getArithmeticInstrCost()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 76 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction({ISD::MUL, ISD::SDIV, ISD::UDIV}, MVT::i32, LibCall); in M68kTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 135 setOperationAction(ISD::SDIV, MVT::i8, Promote); in MSP430TargetLowering()
141 setOperationAction(ISD::SDIV, MVT::i16, LibCall); in MSP430TargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 986 case ISD::SDIV: in canOpTrap()
1860 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 247 case ISD::SDIV: return "sdiv"; in getOperationName()
|
| H A D | FastISel.cpp | 491 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && in selectBinaryOp()
1776 return selectBinaryOp(I, ISD::SDIV); in selectOperator()
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| H A D | LegalizeDAG.cpp | 3702 case ISD::SDIV: { in ExpandNode()
3703 bool isSigned = Node->getOpcode() == ISD::SDIV; in ExpandNode()
4810 case ISD::SDIV: in ConvertNodeToLibcall()
5050 case ISD::SDIV: in PromoteNode()
5072 case ISD::SDIV: in PromoteNode()
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| H A D | SelectionDAG.cpp | 3801 case ISD::SDIV: { in computeKnownBits()
5311 case ISD::SDIV: in isKnownNeverZero()
5938 case ISD::SDIV: in FoldValue()
6028 case ISD::SDIV: in isUndef()
6645 case ISD::SDIV: in getNode()
6992 case ISD::SDIV: in getNode()
7014 case ISD::SDIV: in getNode()
11573 case ISD::SDIV: in isNeutralConstant()
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 189 HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv, SDIV)
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 155 setOperationAction(ISD::SDIV, MVT::i8, Expand); in AVRTargetLowering()
156 setOperationAction(ISD::SDIV, MVT::i16, Expand); in AVRTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 106 setOperationAction(ISD::SDIV, MVT::i32, Expand); in CSKYTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 258 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
304 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
2755 return DAG.getNode(ISD::SDIV, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 524 ISD::SADDSAT, ISD::SDIV, ISD::SDIVREM, ISD::SELECT_CC, in NVPTXTargetLowering()
696 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SRA, ISD::SRL, ISD::MULHS, in NVPTXTargetLowering()
5332 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV; in PerformREMCombine()
|