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Searched refs:ResVT (Results 1 – 25 of 34) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h164 SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
H A DVVPInstrPatternsVec.td598 RegisterClass ResRC, ValueType ResVT,
601 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
609 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
618 RegisterClass ResRC, ValueType ResVT,
620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
621 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "and", "VRAND">;
622 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "xor", "VRXOR">;
623 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "add", "VSUM"#SumSuffix>;
624 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "smax", "VRMAX"#MinMaxSuffix>;
H A DVECustomDAG.cpp562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
576 return getNode(ScalarOC, ResVT, {StartV, ReductionResV}); in getLegalReductionOpVVP()
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
H A DVVPISelLowering.cpp351 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp() local
394 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2495 EVT ResVT = N->getValueType(0); in performVectorExtendToFPCombine() local
2529 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2530 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2534 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2598 EVT ResVT; in performVectorTruncZeroCombine() local
2605 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2609 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
2645 EVT ResVT; in performVectorTruncZeroCombine() local
2650 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2653 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp301 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
1725 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
3146 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
3165 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE_SEQ() local
3191 EVT ResVT = N->getValueType(0); in SplitVecOp_VP_REDUCE() local
3215 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
3274 EVT ResVT = N->getValueType(0); in SplitVecOp_INSERT_SUBVECTOR() local
3958 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
4020 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_TO_XINT_SAT() local
4682 EVT ResVT = N->getValueType(0); in WidenVecRes_OverflowOp() local
[all …]
H A DLegalizeIntegerTypes.cpp340 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
2446 EVT ResVT = N->getValueType(0); in PromoteIntOp_VECREDUCE() local
2494 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2495 return DAG.getNode(Opcode, SDLoc(N), ResVT, Op); in PromoteIntOp_VECREDUCE()
2500 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
5543 EVT ResVT = V0.getValueType(); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local
5545 DAG.getVTList(ResVT, ResVT), V0, V1); in PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE()
5922 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
5925 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
5926 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
[all …]
H A DSelectionDAG.cpp2023 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
2024 return getStepVector(DL, ResVT, One); in getStepVector()
2028 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
2029 if (ResVT.isScalableVector()) in getStepVector()
2031 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
2035 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
2038 return getBuildVector(ResVT, DL, OpsStepConstants); in getStepVector()
12155 EVT ResVT = N->getValueType(0); in UnrollVectorOverflowOp() local
12157 EVT ResEltVT = ResVT.getVectorElementType(); in UnrollVectorOverflowOp()
12162 unsigned NE = ResVT.getVectorNumElements(); in UnrollVectorOverflowOp()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5693 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
5701 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
5702 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
5739 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
5740 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
5853 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
5855 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
5858 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceINTRINSIC_W_CHAIN()
5859 EVT EltVT = ResVT.getVectorElementType(); in ReplaceINTRINSIC_W_CHAIN()
5943 DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceINTRINSIC_W_CHAIN()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1759 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedReductionCost() local
1765 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedReductionCost()
1774 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedReductionCost()
1794 EVT ResVT = TLI->getValueType(DL, ResTy); in getMulAccReductionCost() local
1796 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getMulAccReductionCost()
1805 unsigned RevVTSize = ResVT.getSizeInBits(); in getMulAccReductionCost()
H A DARMISelLowering.cpp17078 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
17153 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
17158 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17190 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17252 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17255 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17271 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17274 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17286 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
17289 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMISelLowering.h619 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1796 if (ResVT != MVT::nxv2i1 && ResVT != MVT::nxv4i1 && ResVT != MVT::nxv8i1 && in shouldExpandGetActiveLaneMask()
1797 ResVT != MVT::nxv16i1 && ResVT != MVT::v2i1 && ResVT != MVT::v4i1 && in shouldExpandGetActiveLaneMask()
1798 ResVT != MVT::v8i1 && ResVT != MVT::v16i1) in shouldExpandGetActiveLaneMask()
5480 EVT ResVT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
20834 EVT ResVT; in trySimplifySrlAddToRshrnb() local
20836 ResVT = MVT::nxv16i8; in trySimplifySrlAddToRshrnb()
20838 ResVT = MVT::nxv8i16; in trySimplifySrlAddToRshrnb()
20840 ResVT = MVT::nxv4i32; in trySimplifySrlAddToRshrnb()
20875 EVT ResVT = N->getValueType(0); in performUzpCombine() local
20934 if (ResVT != MVT::v2i32 && ResVT != MVT::v4i16 && ResVT != MVT::v8i8) in performUzpCombine()
[all …]
H A DAArch64ISelLowering.h751 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h356 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DSIISelLowering.cpp1867 bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
1869 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5511 auto ResVT = DAG.GetSplitDestVTs(VT); in splitTernaryVectorOp() local
5513 SDValue OpLo = DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, in splitTernaryVectorOp()
5515 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
13081 EVT ResVT = N->getValueType(0); in performExtractVectorEltCombine() local
13092 return DAG.getNode(Vec.getOpcode(), SL, ResVT, Elt); in performExtractVectorEltCombine()
13123 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, in performExtractVectorEltCombine()
13181 if (VecEltVT == ResVT) { in performExtractVectorEltCombine()
13185 assert(ResVT.isScalarInteger()); in performExtractVectorEltCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3809 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3816 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3823 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3839 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
6462 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
6490 return DAG.getUNDEF(ResVT); in combineExtract()
6520 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
6522 if (VT != ResVT) { in combineExtract()
6524 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
6560 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h475 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h169 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DHexagonISelLowering.cpp2163 bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2165 assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType()); in isExtractSubvectorCheap()
2166 if (!ResVT.isSimple() || !SrcVT.isSimple()) in isExtractSubvectorCheap()
2169 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp9075 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
9077 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
9143 MVT ResVT = Op.getSimpleValueType(); in LowerCONCAT_VECTORSvXi1() local
9182 SDValue Vec = Zeros ? DAG.getConstant(0, dl, ResVT) : DAG.getUNDEF(ResVT); in LowerCONCAT_VECTORSvXi1()
20695 MVT ResVT = MVT::v4i32; in LowerFP_TO_INT() local
20706 ResVT = MVT::v8i32; in LowerFP_TO_INT()
20736 MVT ResVT = VT; in LowerFP_TO_INT() local
20765 if (ResVT != VT) in LowerFP_TO_INT()
43562 EVT ResVT = in combineVPDPBUSDPattern() local
43565 DP = DAG.getBitcast(ResVT, DP); in combineVPDPBUSDPattern()
[all …]
H A DX86FastISel.cpp3616 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3617 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3618 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3623 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.h1438 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8039 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
8084 ResVT == MVT::f128) in LowerSELECT_CC()
8102 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8121 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8135 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8138 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8145 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8151 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8157 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
15156 EVT ResVT = Val.getValueType(); in combineStoreFPToInt() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h884 SDValue getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal);
888 SDValue getStepVector(const SDLoc &DL, EVT ResVT);

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