17078   EVT ResVT = N->getValueType(0);  in PerformVECREDUCE_ADDCombine()  local
17083   if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD &&  in PerformVECREDUCE_ADDCombine()
17086     SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0));  in PerformVECREDUCE_ADDCombine()
17087     SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1));  in PerformVECREDUCE_ADDCombine()
17088     return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1);  in PerformVECREDUCE_ADDCombine()
17122     if (ResVT != RetTy || N0->getOpcode() != ExtendCode)  in PerformVECREDUCE_ADDCombine()
17131     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
17153     if (ResVT != RetTy)  in PerformVECREDUCE_ADDCombine()
17158             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
17183     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
17190             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
17242     return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17244     return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17252     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17255     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17260     return DAG.getNode(ARMISD::VMLAVps, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17263     return DAG.getNode(ARMISD::VMLAVpu, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17271     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17274     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17278     return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17280     return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17286     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17289     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17293     return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17295     return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17301     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17304     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17322       return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);  in PerformVECREDUCE_ADDCombine()
21232 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()  argument
21234   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
21237   return (Index == 0 || Index == ResVT.getVectorNumElements());  in isExtractSubvectorCheap()