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Searched refs:RegisterClasses (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp138 if (!RegisterClasses.empty()) { in runEnums()
141 assert(RegisterClasses.size() <= 0xffff && in runEnums()
148 for (const auto &RC : RegisterClasses) in runEnums()
1023 for (const auto &RC : RegisterClasses) { in runMCDesc()
1059 for (const auto &RC : RegisterClasses) { in runMCDesc()
1183 if (!RegisterClasses.empty()) { in runTargetHeader()
1187 for (const auto &RC : RegisterClasses) { in runTargetHeader()
1224 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1271 if (!RegisterClasses.empty()) { in runTargetDesc()
1435 for (const auto &RC : RegisterClasses) in runTargetDesc()
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H A DInstrInfoEmitter.cpp363 std::vector<Record *> RegisterClasses = in emitOperandTypeMappings() local
375 {&Operands, &RegisterOperands, &RegisterClasses}) { in emitOperandTypeMappings()
H A DAsmMatcherEmitter.cpp744 RegisterClassesTy RegisterClasses; member in __anonf87813900111::AsmMatcherInfo
1340 RegisterClasses[It.first] = RegisterSetClasses[It.second]; in buildRegisterClasses()
1344 ClassInfo *CI = RegisterClasses[Rec]; in buildRegisterClasses()
1595 Op.Class = RegisterClasses[RegRecord]; in buildInfo()
2510 for (const auto &RC : Info.RegisterClasses) in emitValidateOperandClass()
H A DCodeGenSchedule.cpp1880 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); in collectRegisterFiles() local
1883 for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) { in collectRegisterFiles()
1892 CGRF.Costs.emplace_back(RegisterClasses[I], Cost, AllowMoveElim); in collectRegisterFiles()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td14 list<RegisterClass> RegisterClasses = classes;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td430 // RegisterCategory - This class is a list of RegisterClasses that belong to a