Home
last modified time | relevance | path

Searched refs:RegisterClassHierarchy (Results 1 – 1 of 1) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp64 const CodeGenRegBank &RegisterClassHierarchy) const { in getExplicitlySpecifiedRegisterClasses()
67 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef)); in getExplicitlySpecifiedRegisterClasses()
173 const CodeGenRegBank &RegisterClassHierarchy, in visitRegisterBankClasses() argument
191 visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass, in visitRegisterBankClasses()
202 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
217 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation() local
224 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
251 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
294 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run() local
306 RegisterClassHierarchy, RC, "explicit", in run()
[all …]