64       const CodeGenRegBank &RegisterClassHierarchy) const {  in getExplicitlySpecifiedRegisterClasses()
67       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));  in getExplicitlySpecifiedRegisterClasses()
173     const CodeGenRegBank &RegisterClassHierarchy,  in visitRegisterBankClasses()  argument
185   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {  in visitRegisterBankClasses()
191       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,  in visitRegisterBankClasses()
201     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {  in visitRegisterBankClasses()
202       BitVector BV(RegisterClassHierarchy.getRegClasses().size());  in visitRegisterBankClasses()
217   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();  in emitBaseClassImplementation()  local
224         (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);  in emitBaseClassImplementation()
251        << RegisterClassHierarchy.getRegClasses().size() << ");\n";  in emitBaseClassImplementation()
294   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();  in run()  local
304          Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {  in run()
306           RegisterClassHierarchy, RC, "explicit",  in run()
320   for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {  in run()