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Searched refs:RegClass (Results 1 – 25 of 86) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td555 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
571 wti.RegClass:$rd, GPR:$rs1, vti.RegClass:$rs2,
719 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
753 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
796 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
828 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
867 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1222 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
1230 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
1238 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
[all …]
H A DRISCVInstrInfoVVLPatterns.td1681 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1709 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1727 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1797 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1819 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1850 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1864 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1886 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1908 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
2101 wti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1,
[all …]
H A DRISCVInstrInfoZvk.td507 vti.RegClass:$rs2, vti.RegClass:$rs1,
626 wti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
635 wti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1,
644 wti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$rs1,
653 wti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
662 wti.RegClass:$merge, vti.RegClass:$rs2, GPR:$rs1,
671 wti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$rs1,
722 vti.LMul, vti.RegClass, vti.RegClass>;
746 vti.RegClass, vti.RegClass>;
763 vti.RegClass, vti.RegClass, imm_type>;
[all …]
H A DRISCVInstrInfoVPseudos.td4949 vti.RegClass, vti.RegClass>;
4974 vti.RegClass, vti.RegClass>;
4994 vti.RegClass, ivti.RegClass>;
5079 Vti.RegClass, Vti.RegClass>;
5139 Wti.RegClass, Wti.RegClass, Vti.RegClass>;
5168 Wti.RegClass, Wti.RegClass, Vti.RegClass>;
5225 Wti.RegClass, Vti.RegClass>;
5406 vti.RegClass, vti.RegClass>;
5721 wti.RegClass, vti.RegClass, vti.RegClass>;
5735 wti.RegClass, vti.RegClass, vti.RegClass>;
[all …]
H A DRISCVInstrInfoXSf.td520 payload5, vti.RegClass, kind, op1_kind>;
524 vti.RegClass, kind, op1_kind>;
528 vti.RegClass, kind, op1_kind>;
537 wti.RegClass, vti.RegClass, kind, op1_kind>;
541 wti.RegClass, vti.RegClass, kind, op1_kind>;
545 wti.RegClass, vti.RegClass, kind, op1_kind>;
571 VdInfo.RegClass, VR, Vs2Info.RegClass>;
614 Vti.Log2SEW, Vti.RegClass,
615 Wti.RegClass, Wti.ScalarRegClass>;
625 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrUtils.td974 : ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,
979 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
1000 (node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;
1011 (node t.RegClass:$src1, t.RegClass:$src2,
1040 [(set t.RegClass:$dst, EFLAGS, (node t.RegClass:$src1,
1074 : ITy<0xC1, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2), m,
1076 [(set t.RegClass:$dst, (node t.RegClass:$src1, (i8 imm:$src2)))]>, NDD<ndd> {
1312 : ITy<0xD3, f, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1), m,
1314 [(set t.RegClass:$dst, (node t.RegClass:$src1, CL))]>, NDD<ndd> {
1342 [(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;
[all …]
H A DX86InstrShiftRotate.td354 … [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
355 … [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
363 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))],
364 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]);
390 …: ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$…
396 … [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)))],
405 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL))],
406 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL))]);
542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
568 : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2),
[all …]
H A DX86InstrArithmetic.td274 (outs t.RegClass:$dst),
275 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag t.RegClass:$src1,
1317 [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1),
1318 t.RegClass:$src2))];
1320 [(set t.RegClass:$dst, EFLAGS, (X86and_flag (not t.RegClass:$src1),
1323 (ins t.RegClass:$src1, t.RegClass:$src2), "andn",
1370 def rr : ITy<0xF6, MRMSrcReg, t, (outs t.RegClass:$dst1, t.RegClass:$dst2),
1374 def rm : ITy<0xF6, MRMSrcMem, t, (outs t.RegClass:$dst1, t.RegClass:$dst2),
1380 (outs t.RegClass:$dst1, t.RegClass:$dst2),
1385 (outs t.RegClass:$dst1, t.RegClass:$dst2),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp70 return (DefOpInfo.RegClass == SPIRV::IDRegClassID || in hasType()
71 DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) && in hasType()
72 FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID; in hasType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
99 CopyLocalOpc = WebAssembly::getCopyOpcodeForRegClass(RegClass); in maybeRewriteToFallthrough()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
H A DWebAssemblyRegStackify.cpp104 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
105 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
108 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
111 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
116 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
121 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
638 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
639 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
640 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
650 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
79 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
173 RI.RegClass ? RI.RegClass->LaneMask : LaneBitmask::getAll(); in mapTo()
H A DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
128 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp157 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
159 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
160 assert(RegClass->isAllocatable() && in createVirtualRegister()
165 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
142 Register NewVReg = MRI->createVirtualRegister(RegClass); in INITIALIZE_PASS_DEPENDENCY()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp127 #define DECODE_OPERAND_REG_8(RegClass) \ argument
128 static DecodeStatus Decode##RegClass##RegisterClass( \
134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ argument
151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
163 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
169 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
174 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
790 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; in getInstruction()
1121 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; in convertMIMGInst()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h309 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
315 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass()
405 Bitfield::set<RegClass>(Storage, RC + 1); in setRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td10 // as InstructionSelector RegClass checking code relies on them
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1886 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1887 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1953 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2012 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2013 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2014 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2126 const TargetRegisterClass *RegClass = in createEntryPHI() local
2265 Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass); in createIfRegion()
2401 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
[all …]
H A DGCNDPPCombine.cpp196 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
197 if (RegClass == -1) in getOperandSize()
201 return TRI->getRegSizeInBits(*TRI->getRegClass(RegClass)); in getOperandSize()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp131 bool validateRegister(Record *Reg, Record *RegClass);
151 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
153 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
155 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp542 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
723 (FrameReg.isVirtual() || RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
727 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
763 return Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h97 const TargetRegisterClass &RegClass);
113 const TargetRegisterClass &RegClass,

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