127 #define DECODE_OPERAND_REG_8(RegClass)                                         \  argument
128   static DecodeStatus Decode##RegClass##RegisterClass(                         \
134         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth)                                \  argument
151   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
157 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)                             \  argument
158   DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth,                   \
162 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)                            \  argument
163   DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
168 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)                           \  argument
169   DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
173 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)                         \  argument
174   DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
181 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)           \  argument
182   DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm,      \
190 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)          \  argument
191   DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth,           \
194 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)  \  argument
195   DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9,         \
790               MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;  in getInstruction()
1121     auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;  in convertMIMGInst()
1147     auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;  in convertMIMGInst()