| /freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 65 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
225 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
878 const auto &Regs = RegBank.getRegisters(); in runMCDesc()
911 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc()
1140 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1654 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1732 RegBank.getRegCategories(); in runTargetDesc()
1810 runEnums(OS, Target, RegBank); in run()
1813 runMCDesc(OS, Target, RegBank); in run()
1816 runTargetHeader(OS, Target, RegBank); in run()
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| H A D | CodeGenRegisters.cpp | 187 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
442 RegUnits.set(RegBank.newRegUnit(this)); in computeSubRegs()
553 SubReg.second->computeSuperRegs(RegBank); in computeSuperRegs()
570 TopoSig = RegBank.getTopoSig(Id); in computeSuperRegs()
580 SR->addSubRegsPreOrder(OSet, RegBank); in addSubRegsPreOrder()
987 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
1033 RC.inheritProperties(RegBank); in computeSubClasses()
1050 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()
1821 if (Reg->inheritRegUnits(RegBank)) in normalizeWeight()
1822 computeUberWeights(UberSets, RegBank); in normalizeWeight()
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| H A D | CodeGenTarget.cpp | 319 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
373 if (!RegBank) in getRegBank()
374 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); in getRegBank()
375 return *RegBank; in getRegBank()
379 const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank, in getSuperRegForSubReg() argument
382 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
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| H A D | CodeGenTarget.h | 63 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
125 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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| H A D | CodeGenRegisters.h | 255 bool inheritRegUnits(CodeGenRegBank &RegBank);
262 unsigned getWeight(const CodeGenRegBank &RegBank) const;
403 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
454 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
74 assert(Idx == RegBank.getID() && in verify()
129 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
131 return &RegBank; in getRegBankFromConstraints()
271 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
278 PartMapping.RegBank); in hash_value()
525 assert(RegBank && "Register bank not set"); in verify()
536 if (RegBank) in print()
537 OS << *RegBank; in print()
548 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform()
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| H A D | MachineRegisterInfo.cpp | 63 const RegisterBank &RegBank) { in setRegBank() argument
64 VRegInfo[Reg].first = &RegBank; in setRegBank()
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| H A D | MachineVerifier.cpp | 2276 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand() local
2280 if (!RegBank && isFunctionRegBankSelected) { in visitMachineOperand()
2288 if (RegBank && Ty.isValid() && !Ty.isScalableVector() && in visitMachineOperand()
2289 RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) { in visitMachineOperand()
2292 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
2293 << RBI->getMaximumSize(RegBank->getID()) << ") to fit " in visitMachineOperand()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank; member
67 const RegisterBank &RegBank) in PartialMapping()
68 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
472 const RegisterBank &RegBank) const;
480 const RegisterBank &RegBank) const;
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| H A D | RegisterBank.h | 83 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
84 RegBank.print(OS);
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| H A D | MachineRegisterInfo.h | 705 void setRegBank(Register Reg, const RegisterBank &RegBank);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
190 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
356 unsigned RegBank, in selectLoadStoreOpCode() argument
360 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
374 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| H A D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; in checkPartMapping()
480 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 275 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1340 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1901 const RegisterBank &RegBank, in extendLow32IntoHigh32() argument
1913 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32()
2808 const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank; in applyMappingImpl()
3484 unsigned RegBank = AMDGPU::InvalidRegBankID; in getMappingType() local
3491 RegBank = regBankUnion(RegBank, Bank->getID()); in getMappingType()
3492 if (RegBank == AMDGPU::VGPRRegBankID) in getMappingType()
3497 return RegBank; in getMappingType()
4429 unsigned RSrcBank = OpdsMapping[1]->BreakDown[0].RegBank->getID(); in getInstrMapping()
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| H A D | AMDGPUGenRegisterBankInfo.def | 58 // StartIdx, Length, RegBank
288 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 612 Info.D.RegBank = nullptr; in parseRegisterInfo()
619 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
620 if (!RegBank) in parseRegisterInfo()
626 Info.D.RegBank = RegBank; in parseRegisterInfo()
705 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| H A D | MIParser.cpp | 294 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
296 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
1598 const RegisterBank *RegBank = nullptr; in parseRegisterClassOrBank() local
1600 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
1601 if (!RegBank) in parseRegisterClassOrBank()
1611 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1612 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) in parseRegisterClassOrBank()
1614 RegInfo.D.RegBank = RegBank; in parseRegisterClassOrBank()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 46 const RegisterBank *RegBank; member
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
131 Map.RegBank == &RB;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 121 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
610 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 206 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
207 return getRegClass(Ty, RegBank); in getRegClass()
1419 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1423 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1429 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1488 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1493 getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment); in materializeFP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCGenRegisterBankInfo.def | 16 /* StartIdx, Length, RegBank */
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 837 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank, in getInstrMapping()
838 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, in getInstrMapping()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 168 void setRegBank(Register Reg, const RegisterBank *RegBank);
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