64     CodeGenRegBank &RegBank = Target.getRegBank();  in RegisterInfoEmitter()  local
65     RegBank.computeDerivedInfo();  in RegisterInfoEmitter()
93   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
209 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,  in EmitRegUnitPressure()  argument
211   unsigned NumRCs = RegBank.getRegClasses().size();  in EmitRegUnitPressure()
212   unsigned NumSets = RegBank.getNumRegPressureSets();  in EmitRegUnitPressure()
218   for (const auto &RC : RegBank.getRegClasses()) {  in EmitRegUnitPressure()
220     OS << "    {" << RC.getWeight(RegBank) << ", ";  in EmitRegUnitPressure()
225       RC.buildRegUnitSet(RegBank, RegUnits);  in EmitRegUnitPressure()
226       OS << RegBank.getRegUnitSetWeight(RegUnits);  in EmitRegUnitPressure()
237   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
239     if (RegBank.getRegUnit(UnitIdx).Weight > 1)  in EmitRegUnitPressure()
245      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
249     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
251       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);  in EmitRegUnitPressure()
275     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
291     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
303   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();  in EmitRegUnitPressure()
307     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);  in EmitRegUnitPressure()
310       PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);  in EmitRegUnitPressure()
342      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
346   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
348     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])  in EmitRegUnitPressure()
695                                               CodeGenRegBank &RegBank,  in emitComposeSubRegIndices()  argument
697   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndices()
765                                                     CodeGenRegBank &RegBank,  in emitComposeSubRegIndexLaneMask()  argument
768   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndexLaneMask()
872                                CodeGenRegBank &RegBank) {  in runMCDesc()  argument
878   const auto &Regs = RegBank.getRegisters();  in runMCDesc()
880   auto &SubRegIndices = RegBank.getSubRegIndices();  in runMCDesc()
911     Reg.addSubRegsPreOrder(SR, RegBank);  in runMCDesc()
1003   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {  in runMCDesc()
1004     ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();  in runMCDesc()
1015   const auto &RegisterClasses = RegBank.getRegClasses();  in runMCDesc()
1104      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "  in runMCDesc()
1121                                      CodeGenRegBank &RegBank) {  in runTargetHeader()  argument
1140   if (!RegBank.getSubRegIndices().empty()) {  in runTargetHeader()
1176   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetHeader()
1204                                    CodeGenRegBank &RegBank){  in runTargetDesc()  argument
1217   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetDesc()
1218   const auto &SubRegIndices = RegBank.getSubRegIndices();  in runTargetDesc()
1442   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()
1495     emitComposeSubRegIndices(OS, RegBank, ClassName);  in runTargetDesc()
1496     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);  in runTargetDesc()
1550             MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);  in runTargetDesc()
1578   EmitRegUnitPressure(OS, RegBank, ClassName);  in runTargetDesc()
1654   printMask(OS, RegBank.CoveringLanes);  in runTargetDesc()
1660      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"  in runTargetDesc()
1679     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()
1690     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1697       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());  in runTargetDesc()
1698       Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1704     for (auto &Reg : RegBank.getRegisters()) {  in runTargetDesc()
1708     Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1732       RegBank.getRegCategories();  in runTargetDesc()
1808   CodeGenRegBank &RegBank = Target.getRegBank();  in run()  local
1810   runEnums(OS, Target, RegBank);  in run()
1813   runMCDesc(OS, Target, RegBank);  in run()
1816   runTargetHeader(OS, Target, RegBank);  in run()
1819   runTargetDesc(OS, Target, RegBank);  in run()
1826   CodeGenRegBank &RegBank = Target.getRegBank();  in debugDump()  local
1835   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {  in debugDump()
1856     for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {  in debugDump()
1869   for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {  in debugDump()
1876   for (const CodeGenRegister &R : RegBank.getRegisters()) {  in debugDump()