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Searched refs:Reg0 (Results 1 – 25 of 25) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h121 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
125 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
127 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp462 unsigned Reg0 = in emitPrologue() local
468 std::swap(Reg0, Reg1); in emitPrologue()
471 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
484 std::swap(Reg0, Reg1); in emitPrologue()
487 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
196 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
237 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
251 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII() argument
[all …]
H A DMipsMCCodeEmitter.cpp97 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
102 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
103 if (Reg0 < Reg1) in LowerCompactBranch()
106 if (Reg0 >= Reg1) in LowerCompactBranch()
110 if (Reg1 >= Reg0) in LowerCompactBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
234 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
240 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
845 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
847 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
849 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
851 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp190 Register Reg0 = MI.getOperand(0).getReg(); in isRedundantNewDataDest() local
195 if (Reg1 == Reg0) in isRedundantNewDataDest()
200 !MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0) in isRedundantNewDataDest()
H A DX86ExpandPseudo.cpp467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
473 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
505 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
520 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()
H A DX86InstrInfo.cpp7413 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
7423 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
7424 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h704 uint16_t Reg0 = 0; variable
712 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
718 return Reg0;
723 return Reg0; in isValid()
729 Reg0 = Reg1;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2192 Ops.push_back(Reg0); in SelectVLD()
2378 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2397 Ops.push_back(Reg0); in SelectVST()
2507 Ops.push_back(Reg0); in SelectVLDSTLane()
3051 Ops.push_back(Reg0); in SelectVLDDup()
3374 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3385 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3809 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
3813 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select()
3828 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
[all …]
H A DThumb2SizeReduction.cpp754 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
760 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
766 if (Reg1 != Reg0) in ReduceTo2Addr()
773 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
778 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
785 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
337 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp228 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
250 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
264 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp302 Register Reg0 = Op0.getReg(); in legalizeCustom() local
308 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
313 Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2446 Register Reg0 = getOperand(0).getReg(); in getFirst2RegLLTs() local
2448 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst2RegLLTs()
2454 Register Reg0 = getOperand(0).getReg(); in getFirst3RegLLTs() local
2457 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst3RegLLTs()
2464 Register Reg0 = getOperand(0).getReg(); in getFirst4RegLLTs() local
2469 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst4RegLLTs()
2476 Register Reg0 = getOperand(0).getReg(); in getFirst5RegLLTs() local
2482 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst5RegLLTs()
H A DTargetInstrInfo.cpp185 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
205 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
208 Reg0 = Reg2; in commuteInstructionImpl()
210 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
213 Reg0 = Reg1; in commuteInstructionImpl()
227 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2719 Register Reg0; in valuesIdentical() local
2720 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2721 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2731 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2737 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1303 Register Reg0 = MO0.getReg(); in findAndSortDefOperandIndexes() local
1305 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp193 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
216 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
230 CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1)); in selectInlineAsm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1462 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1465 printRegName(O, Reg0); in printVectorListTwo()
1475 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1478 printRegName(O, Reg0); in printVectorListTwoSpaced()
1530 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1533 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1577 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1580 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1190 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1193 .addImm(Reg0) in InsertSEH()
1203 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1205 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1211 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1244 .addImm(Reg0) in InsertSEH()
1252 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
1254 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1260 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1289 .addImm(Reg0) in InsertSEH()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp968 Register Reg0 = UseMI->getOperand(0).getReg(); in foldOperand() local
970 if (TRI->isAGPR(*MRI, Reg0) && TRI->isVGPR(*MRI, Reg1)) in foldOperand()
972 else if (TRI->isVGPR(*MRI, Reg0) && TRI->isAGPR(*MRI, Reg1)) in foldOperand()
974 else if (ST->hasGFX90AInsts() && TRI->isAGPR(*MRI, Reg0) && in foldOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1981 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
1983 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0); in loadImmediate()
1985 .addReg(Reg0).addImm(Value >> 32); in loadImmediate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1143 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1153 if (Reg0 == Reg1) { in commuteInstructionImpl()
1173 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1176 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()